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Commit afa9fdc2 authored by FUJITA Tomonori's avatar FUJITA Tomonori Committed by Ingo Molnar
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iommu: remove fullflush and nofullflush in IOMMU generic option 

This patch against tip/x86/iommu virtually reverts
2842e5bf. But just reverting the
commit breaks AMD IOMMU so this patch also includes some fixes.

The above commit adds new two options to x86 IOMMU generic kernel boot
options, fullflush and nofullflush. But such change that affects all
the IOMMUs needs more discussion (all IOMMU parties need the chance to
discuss it):

http://lkml.org/lkml/2008/9/19/106



Signed-off-by: default avatarFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent ed6dc498

Documentation/kernel-parameters.txt

+5 −4
Original line number Diff line number Diff line
@@ -284,6 +284,11 @@ and is between 256 and 4096 characters. It is defined in the file 
			isolate - enable device isolation (each device, as far

			          as possible, will get its own protection

			          domain)

			fullflush - enable flushing of IO/TLB entries when

				    they are unmapped. Otherwise they are

				    flushed before they will be reused, which

				    is a lot of faster



	amd_iommu_size= [HW,X86-64]

			Define the size of the aperture for the AMD IOMMU

			driver. Possible values are:
@@ -893,10 +898,6 @@ and is between 256 and 4096 characters. It is defined in the file 
		nomerge

		forcesac

		soft

		fullflush

			Flush IO/TLB at every deallocation

		nofullflush

			Flush IO/TLB only when addresses are reused (default)





	intel_iommu=	[DMAR] Intel IOMMU driver (DMAR) option

Documentation/x86/x86_64/boot-options.txt

+2 −0
Original line number Diff line number Diff line
@@ -233,6 +233,8 @@ IOMMU (input/output memory management unit) 
  iommu options only relevant to the AMD GART hardware IOMMU:

    <size>             Set the size of the remapping area in bytes.

    allowed            Overwrite iommu off workarounds for specific chipsets.

    fullflush          Flush IOMMU on each allocation (default).

    nofullflush        Don't use IOMMU fullflush.

    leak               Turn on simple iommu leak tracing (only when

                       CONFIG_IOMMU_LEAK is on). Default number of leak pages

                       is 20.

arch/x86/kernel/amd_iommu.c

+2 −2
Original line number Diff line number Diff line
@@ -948,7 +948,7 @@ static dma_addr_t __map_single(struct device *dev, 
	}

	address += offset;



	if (unlikely(dma_dom->need_flush && !iommu_fullflush)) {

	if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {

		iommu_flush_tlb(iommu, dma_dom->domain.id);

		dma_dom->need_flush = false;

	} else if (unlikely(iommu_has_npcache(iommu)))
@@ -985,7 +985,7 @@ static void __unmap_single(struct amd_iommu *iommu, 


	dma_ops_free_addresses(dma_dom, dma_addr, pages);



	if (iommu_fullflush)

	if (amd_iommu_unmap_flush)

		iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);

}

arch/x86/kernel/amd_iommu_init.c

+4 −1
Original line number Diff line number Diff line
@@ -122,6 +122,7 @@ LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings 
					   we find in ACPI */

unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */

int amd_iommu_isolate;			/* if 1, device isolation is enabled */

bool amd_iommu_unmap_flush;		/* if true, flush on every unmap */



LIST_HEAD(amd_iommu_list);		/* list of all AMD IOMMUs in the

					   system */
@@ -1144,7 +1145,7 @@ int __init amd_iommu_init(void) 
	else

		printk("disabled\n");



	if (iommu_fullflush)

	if (amd_iommu_unmap_flush)

		printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");

	else

		printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
@@ -1214,6 +1215,8 @@ static int __init parse_amd_iommu_options(char *str) 
	for (; *str; ++str) {

		if (strncmp(str, "isolate", 7) == 0)

			amd_iommu_isolate = 1;

		if (strncmp(str, "fullflush", 11) == 0)

			amd_iommu_unmap_flush = true;

	}



	return 1;

arch/x86/kernel/pci-dma.c

+0 −13
Original line number Diff line number Diff line
@@ -16,15 +16,6 @@ EXPORT_SYMBOL(dma_ops); 


static int iommu_sac_force __read_mostly;



/*

 * If this is disabled the IOMMU will use an optimized flushing strategy

 * of only flushing when an mapping is reused. With it true the GART is

 * flushed for every mapping. Problem is that doing the lazy flush seems

 * to trigger bugs with some popular PCI cards, in particular 3ware (but

 * has been also also seen with Qlogic at least).

 */

int iommu_fullflush;



#ifdef CONFIG_IOMMU_DEBUG

int panic_on_overflow __read_mostly = 1;

int force_iommu __read_mostly = 1;
@@ -180,10 +171,6 @@ static __init int iommu_setup(char *p) 
		}

		if (!strncmp(p, "nomerge", 7))

			iommu_merge = 0;

		if (!strncmp(p, "fullflush", 8))

			iommu_fullflush = 1;

		if (!strncmp(p, "nofullflush", 11))

			iommu_fullflush = 0;

		if (!strncmp(p, "forcesac", 8))

			iommu_sac_force = 1;

		if (!strncmp(p, "allowdac", 8))