Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit af9810ea authored by Shannon Nelson's avatar Shannon Nelson Committed by Jeff Kirsher
Browse files

i40e: Reduce range of interrupt reg in reg test



Use a smaller range of test registers in MFP mode as there are fewer
resources than when in SFP mode.

Change-Id: I08424890c3f57b5dde5ee99e99724ce252e0875a
Signed-off-by: default avatarKamil Krawczyk <kamil.krawczyk@intel.com>
Signed-off-by: default avatarShannon Nelson <shannon.nelson@intel.com>
Tested-by: default avatarKavindya Deegala <kavindya.s.deegala@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 981b7545
Loading
Loading
Loading
Loading
+3 −3
Original line number Diff line number Diff line
@@ -70,9 +70,9 @@ struct i40e_diag_reg_test_info i40e_reg_list[] = {
	/* offset               mask         elements   stride */
	{I40E_QTX_CTL(0),       0x0000FFBF,   4, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
	{I40E_PFINT_ITR0(0),    0x00000FFF,   3, I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
	{I40E_PFINT_ITRN(0, 0), 0x00000FFF,  64, I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
	{I40E_PFINT_ITRN(1, 0), 0x00000FFF,  64, I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
	{I40E_PFINT_ITRN(2, 0), 0x00000FFF,  64, I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
	{I40E_PFINT_ITRN(0, 0), 0x00000FFF,   8, I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
	{I40E_PFINT_ITRN(1, 0), 0x00000FFF,   8, I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
	{I40E_PFINT_ITRN(2, 0), 0x00000FFF,   8, I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
	{I40E_PFINT_STAT_CTL0,  0x0000000C,   1, 0},
	{I40E_PFINT_LNKLST0,    0x00001FFF,   1, 0},
	{I40E_PFINT_LNKLSTN(0), 0x000007FF,  64, I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},