ARM: 6703/1: SPEAr: update clk API support (af89fd81) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/mach-spear3xx/clock.c

+366 −65

Original line number	Original line	Diff line number	Diff line
	@@ -60,12 +60,22 @@ static struct pll_clk_config pll1_config = {
	.masks = &pll1_masks,		.masks = &pll1_masks,
	};		};

			/* pll rate configuration table, in ascending order of rates */
			struct pll_rate_tbl pll_rtbl[] = {
			{.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
			{.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
			};

	/* PLL1 clock */		/* PLL1 clock */
	static struct clk pll1_clk = {		static struct clk pll1_clk = {
			.flags = ENABLED_ON_INIT,
	.pclk = &osc_24m_clk,		.pclk = &osc_24m_clk,
	.en_reg = PLL1_CTR,		.en_reg = PLL1_CTR,
	.en_reg_bit = PLL_ENABLE,		.en_reg_bit = PLL_ENABLE,
			.calc_rate = &pll_calc_rate,
	.recalc = &pll_clk_recalc,		.recalc = &pll_clk_recalc,
			.set_rate = &pll_clk_set_rate,
			.rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
	.private_data = &pll1_config,		.private_data = &pll1_config,
	};		};

	@@ -103,11 +113,22 @@ static struct bus_clk_config ahb_config = {
	.masks = &ahb_masks,		.masks = &ahb_masks,
	};		};

			/* ahb rate configuration table, in ascending order of rates */
			struct bus_rate_tbl bus_rtbl[] = {
			{.div = 3}, /* == parent divided by 4 */
			{.div = 2}, /* == parent divided by 3 */
			{.div = 1}, /* == parent divided by 2 */
			{.div = 0}, /* == parent divided by 1 */
			};

	/* ahb clock */		/* ahb clock */
	static struct clk ahb_clk = {		static struct clk ahb_clk = {
	.flags = ALWAYS_ENABLED,		.flags = ALWAYS_ENABLED,
	.pclk = &pll1_clk,		.pclk = &pll1_clk,
			.calc_rate = &bus_calc_rate,
	.recalc = &bus_clk_recalc,		.recalc = &bus_clk_recalc,
			.set_rate = &bus_clk_set_rate,
			.rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
	.private_data = &ahb_config,		.private_data = &ahb_config,
	};		};

	@@ -123,22 +144,40 @@ static struct aux_clk_masks aux_masks = {
	.yscale_sel_shift = AUX_YSCALE_SHIFT,		.yscale_sel_shift = AUX_YSCALE_SHIFT,
	};		};

	/* uart configurations */		/* uart synth configurations */
	static struct aux_clk_config uart_config = {		static struct aux_clk_config uart_synth_config = {
	.synth_reg = UART_CLK_SYNT,		.synth_reg = UART_CLK_SYNT,
	.masks = &aux_masks,		.masks = &aux_masks,
	};		};

			/* aux rate configuration table, in ascending order of rates */
			struct aux_rate_tbl aux_rtbl[] = {
			/* For PLL1 = 332 MHz */
			{.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
			{.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
			{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
			};

			/* uart synth clock */
			static struct clk uart_synth_clk = {
			.en_reg = UART_CLK_SYNT,
			.en_reg_bit = AUX_SYNT_ENB,
			.pclk = &pll1_clk,
			.calc_rate = &aux_calc_rate,
			.recalc = &aux_clk_recalc,
			.set_rate = &aux_clk_set_rate,
			.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
			.private_data = &uart_synth_config,
			};

	/* uart parents */		/* uart parents */
	static struct pclk_info uart_pclk_info[] = {		static struct pclk_info uart_pclk_info[] = {
	{		{
	.pclk = &pll1_clk,		.pclk = &uart_synth_clk,
	.pclk_mask = AUX_CLK_PLL1_MASK,		.pclk_val = AUX_CLK_PLL1_VAL,
	.scalable = 1,
	}, {		}, {
	.pclk = &pll3_48m_clk,		.pclk = &pll3_48m_clk,
	.pclk_mask = AUX_CLK_PLL3_MASK,		.pclk_val = AUX_CLK_PLL3_VAL,
	.scalable = 0,
	},		},
	};		};

	@@ -156,26 +195,35 @@ static struct clk uart_clk = {
	.en_reg_bit = UART_CLK_ENB,		.en_reg_bit = UART_CLK_ENB,
	.pclk_sel = &uart_pclk_sel,		.pclk_sel = &uart_pclk_sel,
	.pclk_sel_shift = UART_CLK_SHIFT,		.pclk_sel_shift = UART_CLK_SHIFT,
	.recalc = &aux_clk_recalc,		.recalc = &follow_parent,
	.private_data = &uart_config,
	};		};

	/* firda configurations */		/* firda configurations */
	static struct aux_clk_config firda_config = {		static struct aux_clk_config firda_synth_config = {
	.synth_reg = FIRDA_CLK_SYNT,		.synth_reg = FIRDA_CLK_SYNT,
	.masks = &aux_masks,		.masks = &aux_masks,
	};		};

			/* firda synth clock */
			static struct clk firda_synth_clk = {
			.en_reg = FIRDA_CLK_SYNT,
			.en_reg_bit = AUX_SYNT_ENB,
			.pclk = &pll1_clk,
			.calc_rate = &aux_calc_rate,
			.recalc = &aux_clk_recalc,
			.set_rate = &aux_clk_set_rate,
			.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
			.private_data = &firda_synth_config,
			};

	/* firda parents */		/* firda parents */
	static struct pclk_info firda_pclk_info[] = {		static struct pclk_info firda_pclk_info[] = {
	{		{
	.pclk = &pll1_clk,		.pclk = &firda_synth_clk,
	.pclk_mask = AUX_CLK_PLL1_MASK,		.pclk_val = AUX_CLK_PLL1_VAL,
	.scalable = 1,
	}, {		}, {
	.pclk = &pll3_48m_clk,		.pclk = &pll3_48m_clk,
	.pclk_mask = AUX_CLK_PLL3_MASK,		.pclk_val = AUX_CLK_PLL3_VAL,
	.scalable = 0,
	},		},
	};		};

	@@ -193,84 +241,155 @@ static struct clk firda_clk = {
	.en_reg_bit = FIRDA_CLK_ENB,		.en_reg_bit = FIRDA_CLK_ENB,
	.pclk_sel = &firda_pclk_sel,		.pclk_sel = &firda_pclk_sel,
	.pclk_sel_shift = FIRDA_CLK_SHIFT,		.pclk_sel_shift = FIRDA_CLK_SHIFT,
	.recalc = &aux_clk_recalc,		.recalc = &follow_parent,
	.private_data = &firda_config,		};

			/* gpt synthesizer masks */
			static struct gpt_clk_masks gpt_masks = {
			.mscale_sel_mask = GPT_MSCALE_MASK,
			.mscale_sel_shift = GPT_MSCALE_SHIFT,
			.nscale_sel_mask = GPT_NSCALE_MASK,
			.nscale_sel_shift = GPT_NSCALE_SHIFT,
			};

			/* gpt rate configuration table, in ascending order of rates */
			struct gpt_rate_tbl gpt_rtbl[] = {
			/* For pll1 = 332 MHz */
			{.mscale = 4, .nscale = 0}, /* 41.5 MHz */
			{.mscale = 2, .nscale = 0}, /* 55.3 MHz */
			{.mscale = 1, .nscale = 0}, /* 83 MHz */
			};

			/* gpt0 synth clk config*/
			static struct gpt_clk_config gpt0_synth_config = {
			.synth_reg = PRSC1_CLK_CFG,
			.masks = &gpt_masks,
			};

			/* gpt synth clock */
			static struct clk gpt0_synth_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &pll1_clk,
			.calc_rate = &gpt_calc_rate,
			.recalc = &gpt_clk_recalc,
			.set_rate = &gpt_clk_set_rate,
			.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
			.private_data = &gpt0_synth_config,
	};		};

	/* gpt parents */		/* gpt parents */
	static struct pclk_info gpt_pclk_info[] = {		static struct pclk_info gpt0_pclk_info[] = {
	{		{
	.pclk = &pll1_clk,		.pclk = &gpt0_synth_clk,
	.pclk_mask = AUX_CLK_PLL1_MASK,		.pclk_val = AUX_CLK_PLL1_VAL,
	.scalable = 1,
	}, {		}, {
	.pclk = &pll3_48m_clk,		.pclk = &pll3_48m_clk,
	.pclk_mask = AUX_CLK_PLL3_MASK,		.pclk_val = AUX_CLK_PLL3_VAL,
	.scalable = 0,
	},		},
	};		};

	/* gpt parent select structure */		/* gpt parent select structure */
	static struct pclk_sel gpt_pclk_sel = {		static struct pclk_sel gpt0_pclk_sel = {
	.pclk_info = gpt_pclk_info,		.pclk_info = gpt0_pclk_info,
	.pclk_count = ARRAY_SIZE(gpt_pclk_info),		.pclk_count = ARRAY_SIZE(gpt0_pclk_info),
	.pclk_sel_reg = PERIP_CLK_CFG,		.pclk_sel_reg = PERIP_CLK_CFG,
	.pclk_sel_mask = GPT_CLK_MASK,		.pclk_sel_mask = GPT_CLK_MASK,
	};		};

	/* gpt synthesizer masks */		/* gpt0 timer clock */
	static struct gpt_clk_masks gpt_masks = {		static struct clk gpt0_clk = {
	.mscale_sel_mask = GPT_MSCALE_MASK,		.flags = ALWAYS_ENABLED,
	.mscale_sel_shift = GPT_MSCALE_SHIFT,		.pclk_sel = &gpt0_pclk_sel,
	.nscale_sel_mask = GPT_NSCALE_MASK,		.pclk_sel_shift = GPT0_CLK_SHIFT,
	.nscale_sel_shift = GPT_NSCALE_SHIFT,		.recalc = &follow_parent,
	};		};

	/* gpt0 configurations */		/* gpt1 synth clk configurations */
	static struct gpt_clk_config gpt0_config = {		static struct gpt_clk_config gpt1_synth_config = {
	.synth_reg = PRSC1_CLK_CFG,		.synth_reg = PRSC2_CLK_CFG,
	.masks = &gpt_masks,		.masks = &gpt_masks,
	};		};

	/* gpt0 timer clock */		/* gpt1 synth clock */
	static struct clk gpt0_clk = {		static struct clk gpt1_synth_clk = {
	.flags = ALWAYS_ENABLED,		.flags = ALWAYS_ENABLED,
	.pclk_sel = &gpt_pclk_sel,		.pclk = &pll1_clk,
	.pclk_sel_shift = GPT0_CLK_SHIFT,		.calc_rate = &gpt_calc_rate,
	.recalc = &gpt_clk_recalc,		.recalc = &gpt_clk_recalc,
	.private_data = &gpt0_config,		.set_rate = &gpt_clk_set_rate,
			.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
			.private_data = &gpt1_synth_config,
	};		};

	/* gpt1 configurations */		static struct pclk_info gpt1_pclk_info[] = {
	static struct gpt_clk_config gpt1_config = {		{
	.synth_reg = PRSC2_CLK_CFG,		.pclk = &gpt1_synth_clk,
	.masks = &gpt_masks,		.pclk_val = AUX_CLK_PLL1_VAL,
			}, {
			.pclk = &pll3_48m_clk,
			.pclk_val = AUX_CLK_PLL3_VAL,
			},
			};

			/* gpt parent select structure */
			static struct pclk_sel gpt1_pclk_sel = {
			.pclk_info = gpt1_pclk_info,
			.pclk_count = ARRAY_SIZE(gpt1_pclk_info),
			.pclk_sel_reg = PERIP_CLK_CFG,
			.pclk_sel_mask = GPT_CLK_MASK,
	};		};

	/* gpt1 timer clock */		/* gpt1 timer clock */
	static struct clk gpt1_clk = {		static struct clk gpt1_clk = {
	.en_reg = PERIP1_CLK_ENB,		.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = GPT1_CLK_ENB,		.en_reg_bit = GPT1_CLK_ENB,
	.pclk_sel = &gpt_pclk_sel,		.pclk_sel = &gpt1_pclk_sel,
	.pclk_sel_shift = GPT1_CLK_SHIFT,		.pclk_sel_shift = GPT1_CLK_SHIFT,
	.recalc = &gpt_clk_recalc,		.recalc = &follow_parent,
	.private_data = &gpt1_config,
	};		};

	/* gpt2 configurations */		/* gpt2 synth clk configurations */
	static struct gpt_clk_config gpt2_config = {		static struct gpt_clk_config gpt2_synth_config = {
	.synth_reg = PRSC3_CLK_CFG,		.synth_reg = PRSC3_CLK_CFG,
	.masks = &gpt_masks,		.masks = &gpt_masks,
	};		};

			/* gpt1 synth clock */
			static struct clk gpt2_synth_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &pll1_clk,
			.calc_rate = &gpt_calc_rate,
			.recalc = &gpt_clk_recalc,
			.set_rate = &gpt_clk_set_rate,
			.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
			.private_data = &gpt2_synth_config,
			};

			static struct pclk_info gpt2_pclk_info[] = {
			{
			.pclk = &gpt2_synth_clk,
			.pclk_val = AUX_CLK_PLL1_VAL,
			}, {
			.pclk = &pll3_48m_clk,
			.pclk_val = AUX_CLK_PLL3_VAL,
			},
			};

			/* gpt parent select structure */
			static struct pclk_sel gpt2_pclk_sel = {
			.pclk_info = gpt2_pclk_info,
			.pclk_count = ARRAY_SIZE(gpt2_pclk_info),
			.pclk_sel_reg = PERIP_CLK_CFG,
			.pclk_sel_mask = GPT_CLK_MASK,
			};

	/* gpt2 timer clock */		/* gpt2 timer clock */
	static struct clk gpt2_clk = {		static struct clk gpt2_clk = {
	.en_reg = PERIP1_CLK_ENB,		.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = GPT2_CLK_ENB,		.en_reg_bit = GPT2_CLK_ENB,
	.pclk_sel = &gpt_pclk_sel,		.pclk_sel = &gpt2_pclk_sel,
	.pclk_sel_shift = GPT2_CLK_SHIFT,		.pclk_sel_shift = GPT2_CLK_SHIFT,
	.recalc = &gpt_clk_recalc,		.recalc = &follow_parent,
	.private_data = &gpt2_config,
	};		};

	/* clock derived from pll3 clk */		/* clock derived from pll3 clk */
	@@ -290,13 +409,6 @@ static struct clk usbd_clk = {
	.recalc = &follow_parent,		.recalc = &follow_parent,
	};		};

	/* clcd clock */
	static struct clk clcd_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk = &pll3_48m_clk,
	.recalc = &follow_parent,
	};

	/* clock derived from ahb clk */		/* clock derived from ahb clk */
	/* apb masks structure */		/* apb masks structure */
	static struct bus_clk_masks apb_masks = {		static struct bus_clk_masks apb_masks = {
	@@ -314,7 +426,10 @@ static struct bus_clk_config apb_config = {
	static struct clk apb_clk = {		static struct clk apb_clk = {
	.flags = ALWAYS_ENABLED,		.flags = ALWAYS_ENABLED,
	.pclk = &ahb_clk,		.pclk = &ahb_clk,
			.calc_rate = &bus_calc_rate,
	.recalc = &bus_clk_recalc,		.recalc = &bus_clk_recalc,
			.set_rate = &bus_clk_set_rate,
			.rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
	.private_data = &apb_config,		.private_data = &apb_config,
	};		};

	@@ -375,8 +490,17 @@ static struct clk adc_clk = {
	.recalc = &follow_parent,		.recalc = &follow_parent,
	};		};

			#if defined(CONFIG_MACH_SPEAR310) \|\| defined(CONFIG_MACH_SPEAR320)
			/* emi clock */
			static struct clk emi_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &ahb_clk,
			.recalc = &follow_parent,
			};
			#endif

	/* ssp clock */		/* ssp clock */
	static struct clk ssp_clk = {		static struct clk ssp0_clk = {
	.pclk = &apb_clk,		.pclk = &apb_clk,
	.en_reg = PERIP1_CLK_ENB,		.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = SSP_CLK_ENB,		.en_reg_bit = SSP_CLK_ENB,
	@@ -393,6 +517,137 @@ static struct clk gpio_clk = {

	static struct clk dummy_apb_pclk;		static struct clk dummy_apb_pclk;

			#if defined(CONFIG_MACH_SPEAR300) \|\| defined(CONFIG_MACH_SPEAR310) \|\| \
			defined(CONFIG_MACH_SPEAR320)
			/* fsmc clock */
			static struct clk fsmc_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &ahb_clk,
			.recalc = &follow_parent,
			};
			#endif

			/* common clocks to spear310 and spear320 */
			#if defined(CONFIG_MACH_SPEAR310) \|\| defined(CONFIG_MACH_SPEAR320)
			/* uart1 clock */
			static struct clk uart1_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &apb_clk,
			.recalc = &follow_parent,
			};

			/* uart2 clock */
			static struct clk uart2_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &apb_clk,
			.recalc = &follow_parent,
			};
			#endif /* CONFIG_MACH_SPEAR310 \|\| CONFIG_MACH_SPEAR320 */

			/* common clocks to spear300 and spear320 */
			#if defined(CONFIG_MACH_SPEAR300) \|\| defined(CONFIG_MACH_SPEAR320)
			/* clcd clock */
			static struct clk clcd_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &pll3_48m_clk,
			.recalc = &follow_parent,
			};

			/* sdhci clock */
			static struct clk sdhci_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &ahb_clk,
			.recalc = &follow_parent,
			};
			#endif /* CONFIG_MACH_SPEAR300 \|\| CONFIG_MACH_SPEAR320 */

			/* spear300 machine specific clock structures */
			#ifdef CONFIG_MACH_SPEAR300
			/* gpio1 clock */
			static struct clk gpio1_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &apb_clk,
			.recalc = &follow_parent,
			};

			/* keyboard clock */
			static struct clk kbd_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &apb_clk,
			.recalc = &follow_parent,
			};

			#endif

			/* spear310 machine specific clock structures */
			#ifdef CONFIG_MACH_SPEAR310
			/* uart3 clock */
			static struct clk uart3_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &apb_clk,
			.recalc = &follow_parent,
			};

			/* uart4 clock */
			static struct clk uart4_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &apb_clk,
			.recalc = &follow_parent,
			};

			/* uart5 clock */
			static struct clk uart5_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &apb_clk,
			.recalc = &follow_parent,
			};
			#endif

			/* spear320 machine specific clock structures */
			#ifdef CONFIG_MACH_SPEAR320
			/* can0 clock */
			static struct clk can0_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &apb_clk,
			.recalc = &follow_parent,
			};

			/* can1 clock */
			static struct clk can1_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &apb_clk,
			.recalc = &follow_parent,
			};

			/* i2c1 clock */
			static struct clk i2c1_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &ahb_clk,
			.recalc = &follow_parent,
			};

			/* ssp1 clock */
			static struct clk ssp1_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &apb_clk,
			.recalc = &follow_parent,
			};

			/* ssp2 clock */
			static struct clk ssp2_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &apb_clk,
			.recalc = &follow_parent,
			};

			/* pwm clock */
			static struct clk pwm_clk = {
			.flags = ALWAYS_ENABLED,
			.pclk = &apb_clk,
			.recalc = &follow_parent,
			};
			#endif

	/* array of all spear 3xx clock lookups */		/* array of all spear 3xx clock lookups */
	static struct clk_lookup spear_clk_lookups[] = {		static struct clk_lookup spear_clk_lookups[] = {
	{ .con_id = "apb_pclk", .clk = &dummy_apb_pclk},		{ .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
	@@ -400,7 +655,7 @@ static struct clk_lookup spear_clk_lookups[] = {
	{ .con_id = "osc_32k_clk", .clk = &osc_32k_clk},		{ .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
	{ .con_id = "osc_24m_clk", .clk = &osc_24m_clk},		{ .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
	/* clock derived from 32 KHz osc clk */		/* clock derived from 32 KHz osc clk */
	{ .dev_id = "rtc", .clk = &rtc_clk},		{ .dev_id = "rtc-spear", .clk = &rtc_clk},
	/* clock derived from 24 MHz osc clk */		/* clock derived from 24 MHz osc clk */
	{ .con_id = "pll1_clk", .clk = &pll1_clk},		{ .con_id = "pll1_clk", .clk = &pll1_clk},
	{ .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},		{ .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
	@@ -408,18 +663,22 @@ static struct clk_lookup spear_clk_lookups[] = {
	/* clock derived from pll1 clk */		/* clock derived from pll1 clk */
	{ .con_id = "cpu_clk", .clk = &cpu_clk},		{ .con_id = "cpu_clk", .clk = &cpu_clk},
	{ .con_id = "ahb_clk", .clk = &ahb_clk},		{ .con_id = "ahb_clk", .clk = &ahb_clk},
			{ .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
			{ .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
			{ .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
			{ .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk},
			{ .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
	{ .dev_id = "uart", .clk = &uart_clk},		{ .dev_id = "uart", .clk = &uart_clk},
	{ .dev_id = "firda", .clk = &firda_clk},		{ .dev_id = "firda", .clk = &firda_clk},
	{ .dev_id = "gpt0", .clk = &gpt0_clk},		{ .dev_id = "gpt0", .clk = &gpt0_clk},
	{ .dev_id = "gpt1", .clk = &gpt1_clk},		{ .dev_id = "gpt1", .clk = &gpt1_clk},
	{ .dev_id = "gpt2", .clk = &gpt2_clk},		{ .dev_id = "gpt2", .clk = &gpt2_clk},
	/* clock derived from pll3 clk */		/* clock derived from pll3 clk */
	{ .dev_id = "usbh", .clk = &usbh_clk},		{ .con_id = "usbh_clk", .clk = &usbh_clk},
	{ .dev_id = "usbd", .clk = &usbd_clk},		{ .dev_id = "usbd", .clk = &usbd_clk},
	{ .dev_id = "clcd", .clk = &clcd_clk},
	/* clock derived from ahb clk */		/* clock derived from ahb clk */
	{ .con_id = "apb_clk", .clk = &apb_clk},		{ .con_id = "apb_clk", .clk = &apb_clk},
	{ .dev_id = "i2c", .clk = &i2c_clk},		{ .dev_id = "i2c_designware.0", .clk = &i2c_clk},
	{ .dev_id = "dma", .clk = &dma_clk},		{ .dev_id = "dma", .clk = &dma_clk},
	{ .dev_id = "jpeg", .clk = &jpeg_clk},		{ .dev_id = "jpeg", .clk = &jpeg_clk},
	{ .dev_id = "gmac", .clk = &gmac_clk},		{ .dev_id = "gmac", .clk = &gmac_clk},
	@@ -427,8 +686,50 @@ static struct clk_lookup spear_clk_lookups[] = {
	{ .dev_id = "c3", .clk = &c3_clk},		{ .dev_id = "c3", .clk = &c3_clk},
	/* clock derived from apb clk */		/* clock derived from apb clk */
	{ .dev_id = "adc", .clk = &adc_clk},		{ .dev_id = "adc", .clk = &adc_clk},
	{ .dev_id = "ssp", .clk = &ssp_clk},		{ .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
	{ .dev_id = "gpio", .clk = &gpio_clk},		{ .dev_id = "gpio", .clk = &gpio_clk},
			#if defined(CONFIG_MACH_SPEAR310) \|\| defined(CONFIG_MACH_SPEAR320)
			{ .dev_id = "physmap-flash", .clk = &emi_clk},
			#endif
			#if defined(CONFIG_MACH_SPEAR300) \|\| defined(CONFIG_MACH_SPEAR310) \|\| \
			defined(CONFIG_MACH_SPEAR320)
			{ .con_id = "fsmc", .clk = &fsmc_clk},
			#endif

			/* common clocks to spear310 and spear320 */
			#if defined(CONFIG_MACH_SPEAR310) \|\| defined(CONFIG_MACH_SPEAR320)
			{ .dev_id = "uart1", .clk = &uart1_clk},
			{ .dev_id = "uart2", .clk = &uart2_clk},
			#endif

			/* common clock to spear300 and spear320 */
			#if defined(CONFIG_MACH_SPEAR300) \|\| defined(CONFIG_MACH_SPEAR320)
			{ .dev_id = "clcd", .clk = &clcd_clk},
			{ .dev_id = "sdhci", .clk = &sdhci_clk},
			#endif /* CONFIG_MACH_SPEAR300 \|\| CONFIG_MACH_SPEAR320 */

			/* spear300 machine specific clock structures */
			#ifdef CONFIG_MACH_SPEAR300
			{ .dev_id = "gpio1", .clk = &gpio1_clk},
			{ .dev_id = "keyboard", .clk = &kbd_clk},
			#endif

			/* spear310 machine specific clock structures */
			#ifdef CONFIG_MACH_SPEAR310
			{ .dev_id = "uart3", .clk = &uart3_clk},
			{ .dev_id = "uart4", .clk = &uart4_clk},
			{ .dev_id = "uart5", .clk = &uart5_clk},

			#endif
			/* spear320 machine specific clock structures */
			#ifdef CONFIG_MACH_SPEAR320
			{ .dev_id = "c_can_platform.0", .clk = &can0_clk},
			{ .dev_id = "c_can_platform.1", .clk = &can1_clk},
			{ .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
			{ .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
			{ .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
			{ .dev_id = "pwm", .clk = &pwm_clk},
			#endif
	};		};

	void __init clk_init(void)		void __init clk_init(void)

arch/arm/mach-spear3xx/include/mach/misc_regs.h

+3 −2

Original line number	Original line	Diff line number	Diff line
	@@ -63,8 +63,8 @@
	#define GPT1_CLK_SHIFT 11		#define GPT1_CLK_SHIFT 11
	#define GPT2_CLK_SHIFT 12		#define GPT2_CLK_SHIFT 12
	#define GPT_CLK_MASK 0x1		#define GPT_CLK_MASK 0x1
	#define AUX_CLK_PLL3_MASK 0		#define AUX_CLK_PLL3_VAL 0
	#define AUX_CLK_PLL1_MASK 1		#define AUX_CLK_PLL1_VAL 1

	#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)		#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
	/* PERIP1_CLK_ENB register masks */		/* PERIP1_CLK_ENB register masks */
	@@ -113,6 +113,7 @@
	#define RAS3_CLK_SYNT (MISC_BASE + 0x074)		#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
	#define RAS4_CLK_SYNT (MISC_BASE + 0x078)		#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
	/* aux clk synthesiser register masks for irda to ras4 */		/* aux clk synthesiser register masks for irda to ras4 */
			#define AUX_SYNT_ENB 31
	#define AUX_EQ_SEL_SHIFT 30		#define AUX_EQ_SEL_SHIFT 30
	#define AUX_EQ_SEL_MASK 1		#define AUX_EQ_SEL_MASK 1
	#define AUX_EQ1_SEL 0		#define AUX_EQ1_SEL 0

arch/arm/mach-spear6xx/clock.c

+238 −93

File changed.

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arch/arm/mach-spear6xx/include/mach/misc_regs.h

+3 −2

Original line number	Original line	Diff line number	Diff line
	@@ -66,8 +66,8 @@
	#define GPT2_CLK_SHIFT 11		#define GPT2_CLK_SHIFT 11
	#define GPT3_CLK_SHIFT 12		#define GPT3_CLK_SHIFT 12
	#define GPT_CLK_MASK 0x1		#define GPT_CLK_MASK 0x1
	#define AUX_CLK_PLL3_MASK 0		#define AUX_CLK_PLL3_VAL 0
	#define AUX_CLK_PLL1_MASK 1		#define AUX_CLK_PLL1_VAL 1

	#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)		#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
	/* PERIP1_CLK_ENB register masks */		/* PERIP1_CLK_ENB register masks */
	@@ -123,6 +123,7 @@
	#define RAS3_CLK_SYNT (MISC_BASE + 0x074)		#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
	#define RAS4_CLK_SYNT (MISC_BASE + 0x078)		#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
	/* aux clk synthesiser register masks for irda to ras4 */		/* aux clk synthesiser register masks for irda to ras4 */
			#define AUX_SYNT_ENB 31
	#define AUX_EQ_SEL_SHIFT 30		#define AUX_EQ_SEL_SHIFT 30
	#define AUX_EQ_SEL_MASK 1		#define AUX_EQ_SEL_MASK 1
	#define AUX_EQ1_SEL 0		#define AUX_EQ1_SEL 0

arch/arm/plat-spear/clock.c

+567 −138

File changed.

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