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Commit af36e6b6 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
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[TG3]: Add 5755 support



Add support for new chip 5755 which is very similar to 5787.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b30bd282
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+31 −6
Original line number Diff line number Diff line
@@ -225,6 +225,10 @@ static struct pci_device_id tg3_pci_tbl[] = {
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M,
@@ -4557,6 +4561,7 @@ static int tg3_chip_reset(struct tg3 *tp)
	}

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
		tw32(GRC_FASTBOOT_PC, 0);

@@ -6152,6 +6157,9 @@ static int tg3_reset_hw(struct tg3 *tp)
			gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
				     GRC_LCLCTRL_GPIO_OUTPUT3;

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
			gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;

		tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;

		/* GPIO1 must be driven high for eeprom write protect */
@@ -6191,7 +6199,8 @@ static int tg3_reset_hw(struct tg3 *tp)
	}

	/* Enable host coalescing bug fix */
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
		val |= (1 << 29);

	tw32_f(WDMAC_MODE, val);
@@ -6249,6 +6258,9 @@ static int tg3_reset_hw(struct tg3 *tp)
	udelay(100);

	tp->rx_mode = RX_MODE_ENABLE;
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
		tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;

	tw32_f(MAC_RX_MODE, tp->rx_mode);
	udelay(10);

@@ -7907,7 +7919,8 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
  		return 0;
  	}
  
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
		ethtool_op_set_tx_hw_csum(dev, data);
	else
		ethtool_op_set_tx_csum(dev, data);
@@ -8332,7 +8345,8 @@ static int tg3_test_memory(struct tg3 *tp)
	int i;

	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
			mem_tbl = mem_tbl_5755;
		else
			mem_tbl = mem_tbl_5705;
@@ -9310,6 +9324,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
			nvram_cmd |= NVRAM_CMD_LAST;

		if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
		    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
		    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
		    (tp->nvram_jedecnum == JEDEC_ST) &&
		    (nvram_cmd & NVRAM_CMD_FIRST)) {
@@ -10044,6 +10059,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
	    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
		tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
@@ -10053,7 +10069,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
		tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;

	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
			tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
			tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
		} else
@@ -10063,6 +10080,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)
		tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;

@@ -10219,6 +10237,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;

	/* Force the chip into D0. */
	err = tg3_set_power_state(tp, PCI_D0);
	if (err) {
@@ -10274,6 +10295,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
		tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;

	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
	    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
	    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787))
		tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;

@@ -10413,7 +10435,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
	/* All chips before 5787 can get confused if TX buffers
	 * straddle the 4GB address boundary in some cases.
	 */
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
		tp->dev->hard_start_xmit = tg3_start_xmit;
	else
		tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
@@ -11002,6 +11025,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
	case PHY_ID_BCM5752:	return "5752";
	case PHY_ID_BCM5714:	return "5714";
	case PHY_ID_BCM5780:	return "5780";
	case PHY_ID_BCM5755:	return "5755";
	case PHY_ID_BCM5787:	return "5787";
	case PHY_ID_BCM8002:	return "8002/serdes";
	case 0:			return "serdes";
@@ -11350,7 +11374,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
	 * checksumming.
	 */
	if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
			dev->features |= NETIF_F_HW_CSUM;
		else
			dev->features |= NETIF_F_IP_CSUM;
+5 −1
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@
#define   ASIC_REV_5752			 0x06
#define   ASIC_REV_5780			 0x08
#define   ASIC_REV_5714			 0x09
#define   ASIC_REV_5755			 0x0a
#define   ASIC_REV_5787			 0x0b
#define  GET_CHIP_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 8)
#define   CHIPREV_5700_AX		 0x70
@@ -456,6 +457,7 @@
#define  RX_MODE_PROMISC		 0x00000100
#define  RX_MODE_NO_CRC_CHECK		 0x00000200
#define  RX_MODE_KEEP_VLAN_TAG		 0x00000400
#define  RX_MODE_IPV6_CSUM_ENABLE	 0x01000000
#define MAC_RX_STATUS			0x0000046c
#define  RX_STATUS_REMOTE_TX_XOFFED	 0x00000001
#define  RX_STATUS_XOFF_RCVD		 0x00000002
@@ -1340,6 +1342,7 @@
#define  GRC_LCLCTRL_CLEARINT		0x00000002
#define  GRC_LCLCTRL_SETINT		0x00000004
#define  GRC_LCLCTRL_INT_ON_ATTN	0x00000008
#define  GRC_LCLCTRL_GPIO_UART_SEL	0x00000010	/* 5755 only */
#define  GRC_LCLCTRL_USE_SIG_DETECT	0x00000010	/* 5714/5780 only */
#define  GRC_LCLCTRL_USE_EXT_SIG_DETECT	0x00000020	/* 5714/5780 only */
#define  GRC_LCLCTRL_GPIO_INPUT3	0x00000020
@@ -2259,6 +2262,7 @@ struct tg3 {
#define PHY_ID_BCM5752			0x60008100
#define PHY_ID_BCM5714			0x60008340
#define PHY_ID_BCM5780			0x60008350
#define PHY_ID_BCM5755			0xbc050cc0
#define PHY_ID_BCM5787			0xbc050ce0
#define PHY_ID_BCM8002			0x60010140
#define PHY_ID_INVALID			0xffffffff
@@ -2286,7 +2290,7 @@ struct tg3 {
	 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
	 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
	 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
	 (X) == PHY_ID_BCM8002)
	 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM8002)

	struct tg3_hw_stats		*hw_stats;
	dma_addr_t			stats_mapping;
+2 −0
Original line number Diff line number Diff line
@@ -1864,11 +1864,13 @@
#define PCI_DEVICE_ID_TIGON3_5780S	0x166b
#define PCI_DEVICE_ID_TIGON3_5705F	0x166e
#define PCI_DEVICE_ID_TIGON3_5754M	0x1672
#define PCI_DEVICE_ID_TIGON3_5755M	0x1673
#define PCI_DEVICE_ID_TIGON3_5750	0x1676
#define PCI_DEVICE_ID_TIGON3_5751	0x1677
#define PCI_DEVICE_ID_TIGON3_5715	0x1678
#define PCI_DEVICE_ID_TIGON3_5715S	0x1679
#define PCI_DEVICE_ID_TIGON3_5754	0x167a
#define PCI_DEVICE_ID_TIGON3_5755	0x167b
#define PCI_DEVICE_ID_TIGON3_5750M	0x167c
#define PCI_DEVICE_ID_TIGON3_5751M	0x167d
#define PCI_DEVICE_ID_TIGON3_5751F	0x167e