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Commit aeb27748 authored by Benoît Thébaudeau's avatar Benoît Thébaudeau Committed by Linus Walleij
Browse files

gpio/mxc: use the edge_sel feature if available 



Some mxc processors have an edge_sel feature, which allows the IRQ to be
triggered by any edge.

This patch makes use of this feature if available, which skips mxc_flip_edge().

Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Acked-by: default avatarSascha Hauer <kernel@pengutronix.de>
Cc: <linux-arm-kernel@lists.infradead.org>
Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 41920d16

Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt

+1 −1
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ Required properties: 
Example:



gpio0: gpio@73f84000 {

	compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";

	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";

	reg = <0x73f84000 0x4000>;

	interrupts = <50 51>;

	gpio-controller;

arch/arm/boot/dts/imx51.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ 
			};



			gpio1: gpio@73f84000 {

				compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";

				reg = <0x73f84000 0x4000>;

				interrupts = <50 51>;

				gpio-controller;
@@ -137,7 +137,7 @@ 
			};



			gpio2: gpio@73f88000 {

				compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";

				reg = <0x73f88000 0x4000>;

				interrupts = <52 53>;

				gpio-controller;
@@ -147,7 +147,7 @@ 
			};



			gpio3: gpio@73f8c000 {

				compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";

				reg = <0x73f8c000 0x4000>;

				interrupts = <54 55>;

				gpio-controller;
@@ -157,7 +157,7 @@ 
			};



			gpio4: gpio@73f90000 {

				compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";

				reg = <0x73f90000 0x4000>;

				interrupts = <56 57>;

				gpio-controller;

arch/arm/boot/dts/imx53.dtsi

+7 −7
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ 
			};



			gpio1: gpio@53f84000 {

				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";

				reg = <0x53f84000 0x4000>;

				interrupts = <50 51>;

				gpio-controller;
@@ -139,7 +139,7 @@ 
			};



			gpio2: gpio@53f88000 {

				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";

				reg = <0x53f88000 0x4000>;

				interrupts = <52 53>;

				gpio-controller;
@@ -149,7 +149,7 @@ 
			};



			gpio3: gpio@53f8c000 {

				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";

				reg = <0x53f8c000 0x4000>;

				interrupts = <54 55>;

				gpio-controller;
@@ -159,7 +159,7 @@ 
			};



			gpio4: gpio@53f90000 {

				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";

				reg = <0x53f90000 0x4000>;

				interrupts = <56 57>;

				gpio-controller;
@@ -197,7 +197,7 @@ 
			};



			gpio5: gpio@53fdc000 {

				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";

				reg = <0x53fdc000 0x4000>;

				interrupts = <103 104>;

				gpio-controller;
@@ -207,7 +207,7 @@ 
			};



			gpio6: gpio@53fe0000 {

				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";

				reg = <0x53fe0000 0x4000>;

				interrupts = <105 106>;

				gpio-controller;
@@ -217,7 +217,7 @@ 
			};



			gpio7: gpio@53fe4000 {

				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";

				reg = <0x53fe4000 0x4000>;

				interrupts = <107 108>;

				gpio-controller;

arch/arm/boot/dts/imx6q.dtsi

+7 −7
Original line number Diff line number Diff line
@@ -260,7 +260,7 @@ 
			};



			gpio1: gpio@0209c000 {

				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";

				reg = <0x0209c000 0x4000>;

				interrupts = <0 66 0x04 0 67 0x04>;

				gpio-controller;
@@ -270,7 +270,7 @@ 
			};



			gpio2: gpio@020a0000 {

				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";

				reg = <0x020a0000 0x4000>;

				interrupts = <0 68 0x04 0 69 0x04>;

				gpio-controller;
@@ -280,7 +280,7 @@ 
			};



			gpio3: gpio@020a4000 {

				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";

				reg = <0x020a4000 0x4000>;

				interrupts = <0 70 0x04 0 71 0x04>;

				gpio-controller;
@@ -290,7 +290,7 @@ 
			};



			gpio4: gpio@020a8000 {

				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";

				reg = <0x020a8000 0x4000>;

				interrupts = <0 72 0x04 0 73 0x04>;

				gpio-controller;
@@ -300,7 +300,7 @@ 
			};



			gpio5: gpio@020ac000 {

				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";

				reg = <0x020ac000 0x4000>;

				interrupts = <0 74 0x04 0 75 0x04>;

				gpio-controller;
@@ -310,7 +310,7 @@ 
			};



			gpio6: gpio@020b0000 {

				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";

				reg = <0x020b0000 0x4000>;

				interrupts = <0 76 0x04 0 77 0x04>;

				gpio-controller;
@@ -320,7 +320,7 @@ 
			};



			gpio7: gpio@020b4000 {

				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";

				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";

				reg = <0x020b4000 0x4000>;

				interrupts = <0 78 0x04 0 79 0x04>;

				gpio-controller;

arch/arm/mach-imx/mm-imx25.c

+5 −5
Original line number Diff line number Diff line
@@ -90,11 +90,11 @@ static const struct resource imx25_audmux_res[] __initconst = { 


void __init imx25_soc_init(void)

{

	/* i.mx25 has the i.mx31 type gpio */

	mxc_register_gpio("imx31-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);

	mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);

	mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);

	mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);

	/* i.mx25 has the i.mx35 type gpio */

	mxc_register_gpio("imx35-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);

	mxc_register_gpio("imx35-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);

	mxc_register_gpio("imx35-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);

	mxc_register_gpio("imx35-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);



	pinctrl_provide_dummies();

	/* i.mx25 has the i.mx35 type sdma */