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Commit aeb06593 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Convert irq_refounct to struct 



It's overkill on older gens, but it's useful for newer gens.

Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4848405c

drivers/gpu/drm/i915/intel_ringbuffer.c

+8 −8
Original line number Diff line number Diff line
@@ -795,7 +795,7 @@ gen5_ring_get_irq(struct intel_ring_buffer *ring) 
		return false;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (ring->irq_refcount++ == 0) {

	if (ring->irq_refcount.gt++ == 0) {

		dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;

		I915_WRITE(GTIMR, dev_priv->gt_irq_mask);

		POSTING_READ(GTIMR);
@@ -813,7 +813,7 @@ gen5_ring_put_irq(struct intel_ring_buffer *ring) 
	unsigned long flags;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (--ring->irq_refcount == 0) {

	if (--ring->irq_refcount.gt == 0) {

		dev_priv->gt_irq_mask |= ring->irq_enable_mask;

		I915_WRITE(GTIMR, dev_priv->gt_irq_mask);

		POSTING_READ(GTIMR);
@@ -832,7 +832,7 @@ i9xx_ring_get_irq(struct intel_ring_buffer *ring) 
		return false;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (ring->irq_refcount++ == 0) {

	if (ring->irq_refcount.gt++ == 0) {

		dev_priv->irq_mask &= ~ring->irq_enable_mask;

		I915_WRITE(IMR, dev_priv->irq_mask);

		POSTING_READ(IMR);
@@ -850,7 +850,7 @@ i9xx_ring_put_irq(struct intel_ring_buffer *ring) 
	unsigned long flags;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (--ring->irq_refcount == 0) {

	if (--ring->irq_refcount.gt == 0) {

		dev_priv->irq_mask |= ring->irq_enable_mask;

		I915_WRITE(IMR, dev_priv->irq_mask);

		POSTING_READ(IMR);
@@ -869,7 +869,7 @@ i8xx_ring_get_irq(struct intel_ring_buffer *ring) 
		return false;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (ring->irq_refcount++ == 0) {

	if (ring->irq_refcount.gt++ == 0) {

		dev_priv->irq_mask &= ~ring->irq_enable_mask;

		I915_WRITE16(IMR, dev_priv->irq_mask);

		POSTING_READ16(IMR);
@@ -887,7 +887,7 @@ i8xx_ring_put_irq(struct intel_ring_buffer *ring) 
	unsigned long flags;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (--ring->irq_refcount == 0) {

	if (--ring->irq_refcount.gt == 0) {

		dev_priv->irq_mask |= ring->irq_enable_mask;

		I915_WRITE16(IMR, dev_priv->irq_mask);

		POSTING_READ16(IMR);
@@ -980,7 +980,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring) 
	gen6_gt_force_wake_get(dev_priv);



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (ring->irq_refcount++ == 0) {

	if (ring->irq_refcount.gt++ == 0) {

		if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)

			I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |

						GEN6_RENDER_L3_PARITY_ERROR));
@@ -1003,7 +1003,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring) 
	unsigned long flags;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (--ring->irq_refcount == 0) {

	if (--ring->irq_refcount.gt == 0) {

		if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)

			I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);

		else

drivers/gpu/drm/i915/intel_ringbuffer.h

+3 −1
Original line number Diff line number Diff line
@@ -72,7 +72,9 @@ struct intel_ring_buffer { 
	 */

	u32		last_retired_head;



	u32		irq_refcount;		/* protected by dev_priv->irq_lock */

	struct {

		u32	gt;

	} irq_refcount;	/* protected by dev_priv->irq_lock */

	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */

	u32		trace_irq_seqno;

	u32		sync_seqno[I915_NUM_RINGS-1];