Loading arch/powerpc/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -775,6 +775,7 @@ config LOWMEM_CAM_NUM_BOOL Say N here unless you know what you are doing. config LOWMEM_CAM_NUM depends on FSL_BOOKE int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL default 3 Loading arch/powerpc/boot/dts/ksi8560.dts +2 −2 Original line number Diff line number Diff line Loading @@ -57,14 +57,14 @@ bus-frequency = <0>; /* Fixed by bootwrapper */ memory-controller@2000 { compatible = "fsl,8540-memory-controller"; compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <0x12 0x2>; }; L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; compatible = "fsl,mpc8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; /* 32 bytes */ cache-size = <0x40000>; /* L2, 256K */ Loading arch/powerpc/boot/dts/pq2fads.dts +14 −6 Original line number Diff line number Diff line Loading @@ -17,6 +17,14 @@ #address-cells = <1>; #size-cells = <1>; aliases { ethernet0 = &enet0; ethernet1 = &enet1; serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; }; cpus { #address-cells = <1>; #size-cells = <0>; Loading Loading @@ -45,7 +53,7 @@ #size-cells = <1>; reg = <0xf0010100 0x60>; ranges = <0x0 0x0 0xfe000000 0x800000 ranges = <0x0 0x0 0xff800000 0x800000 0x1 0x0 0xf4500000 0x8000 0x8 0x0 0xf8200000 0x8000>; Loading @@ -71,7 +79,7 @@ }; }; pci@f0010800 { pci0: pci@f0010800 { device_type = "pci"; reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>; compatible = "fsl,mpc8280-pci", "fsl,pq2-pci"; Loading Loading @@ -142,7 +150,7 @@ reg = <0x119f0 0x10 0x115f0 0x10>; }; serial@11a00 { serial0: serial@11a00 { device_type = "serial"; compatible = "fsl,mpc8280-scc-uart", "fsl,cpm2-scc-uart"; Loading @@ -153,7 +161,7 @@ fsl,cpm-command = <0x800000>; }; serial@11a20 { serial1: serial@11a20 { device_type = "serial"; compatible = "fsl,mpc8280-scc-uart", "fsl,cpm2-scc-uart"; Loading @@ -164,7 +172,7 @@ fsl,cpm-command = <0x4a00000>; }; ethernet@11320 { enet0: ethernet@11320 { device_type = "network"; compatible = "fsl,mpc8280-fcc-enet", "fsl,cpm2-fcc-enet"; Loading @@ -176,7 +184,7 @@ fsl,cpm-command = <0x16200300>; }; ethernet@11340 { enet1: ethernet@11340 { device_type = "network"; compatible = "fsl,mpc8280-fcc-enet", "fsl,cpm2-fcc-enet"; Loading arch/powerpc/boot/dts/sbc8548.dts +2 −2 Original line number Diff line number Diff line Loading @@ -156,14 +156,14 @@ compatible = "simple-bus"; memory-controller@2000 { compatible = "fsl,8548-memory-controller"; compatible = "fsl,mpc8548-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <0x12 0x2>; }; L2: l2-cache-controller@20000 { compatible = "fsl,8548-l2-cache-controller"; compatible = "fsl,mpc8548-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes cache-size = <0x80000>; // L2, 512K Loading arch/powerpc/boot/dts/sbc8560.dts +2 −2 Original line number Diff line number Diff line Loading @@ -61,14 +61,14 @@ clock-frequency = <0>; memory-controller@2000 { compatible = "fsl,8560-memory-controller"; compatible = "fsl,mpc8560-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <0x12 0x2>; }; L2: l2-cache-controller@20000 { compatible = "fsl,8560-l2-cache-controller"; compatible = "fsl,mpc8560-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes cache-size = <0x40000>; // L2, 256K Loading Loading
arch/powerpc/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -775,6 +775,7 @@ config LOWMEM_CAM_NUM_BOOL Say N here unless you know what you are doing. config LOWMEM_CAM_NUM depends on FSL_BOOKE int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL default 3 Loading
arch/powerpc/boot/dts/ksi8560.dts +2 −2 Original line number Diff line number Diff line Loading @@ -57,14 +57,14 @@ bus-frequency = <0>; /* Fixed by bootwrapper */ memory-controller@2000 { compatible = "fsl,8540-memory-controller"; compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <0x12 0x2>; }; L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; compatible = "fsl,mpc8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; /* 32 bytes */ cache-size = <0x40000>; /* L2, 256K */ Loading
arch/powerpc/boot/dts/pq2fads.dts +14 −6 Original line number Diff line number Diff line Loading @@ -17,6 +17,14 @@ #address-cells = <1>; #size-cells = <1>; aliases { ethernet0 = &enet0; ethernet1 = &enet1; serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; }; cpus { #address-cells = <1>; #size-cells = <0>; Loading Loading @@ -45,7 +53,7 @@ #size-cells = <1>; reg = <0xf0010100 0x60>; ranges = <0x0 0x0 0xfe000000 0x800000 ranges = <0x0 0x0 0xff800000 0x800000 0x1 0x0 0xf4500000 0x8000 0x8 0x0 0xf8200000 0x8000>; Loading @@ -71,7 +79,7 @@ }; }; pci@f0010800 { pci0: pci@f0010800 { device_type = "pci"; reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>; compatible = "fsl,mpc8280-pci", "fsl,pq2-pci"; Loading Loading @@ -142,7 +150,7 @@ reg = <0x119f0 0x10 0x115f0 0x10>; }; serial@11a00 { serial0: serial@11a00 { device_type = "serial"; compatible = "fsl,mpc8280-scc-uart", "fsl,cpm2-scc-uart"; Loading @@ -153,7 +161,7 @@ fsl,cpm-command = <0x800000>; }; serial@11a20 { serial1: serial@11a20 { device_type = "serial"; compatible = "fsl,mpc8280-scc-uart", "fsl,cpm2-scc-uart"; Loading @@ -164,7 +172,7 @@ fsl,cpm-command = <0x4a00000>; }; ethernet@11320 { enet0: ethernet@11320 { device_type = "network"; compatible = "fsl,mpc8280-fcc-enet", "fsl,cpm2-fcc-enet"; Loading @@ -176,7 +184,7 @@ fsl,cpm-command = <0x16200300>; }; ethernet@11340 { enet1: ethernet@11340 { device_type = "network"; compatible = "fsl,mpc8280-fcc-enet", "fsl,cpm2-fcc-enet"; Loading
arch/powerpc/boot/dts/sbc8548.dts +2 −2 Original line number Diff line number Diff line Loading @@ -156,14 +156,14 @@ compatible = "simple-bus"; memory-controller@2000 { compatible = "fsl,8548-memory-controller"; compatible = "fsl,mpc8548-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <0x12 0x2>; }; L2: l2-cache-controller@20000 { compatible = "fsl,8548-l2-cache-controller"; compatible = "fsl,mpc8548-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes cache-size = <0x80000>; // L2, 512K Loading
arch/powerpc/boot/dts/sbc8560.dts +2 −2 Original line number Diff line number Diff line Loading @@ -61,14 +61,14 @@ clock-frequency = <0>; memory-controller@2000 { compatible = "fsl,8560-memory-controller"; compatible = "fsl,mpc8560-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <0x12 0x2>; }; L2: l2-cache-controller@20000 { compatible = "fsl,8560-l2-cache-controller"; compatible = "fsl,mpc8560-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes cache-size = <0x40000>; // L2, 256K Loading