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Commit ae56e418 authored by Odelu Kukatla's avatar Odelu Kukatla
Browse files

ARM: dts: msm: Update CPU clock min frequncy for MSM8937 



MSM8937 CPU minimum frequency is updated to support 960MHz and 768MHz
respectively for big and little cluster , so update the frequency table
and the CPR node to reflect the same.

Change-Id: I32bfa8e2360befb3a4c1dde081afb49fe9e392d4
Signed-off-by: default avatarOdelu Kukatla <okukatla@codeaurora.org>
parent 863822f1

arch/arm/boot/dts/qcom/msm8937-regulator.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -395,7 +395,7 @@ 
		qcom,cpr-init-voltage-step = <10000>;

		qcom,cpr-corner-map = <1 2 3 3 3>;

		qcom,cpr-corner-frequency-map =

				<1 998400000>,

				<1 960000000>,

				<2 1094400000>,

				<3 1248000000>,

				<4 1344000000>,

arch/arm/boot/dts/qcom/msm8937.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -673,14 +673,14 @@ 
				"clk-cci-4", "clk-cci-2";

		qcom,speed0-bin-v0-c0 =

			<          0 0>,

			<  806400000 1>,

			<  768000000 1>,

			<  902400000 2>,

			<  998400000 3>,

			< 1094400000 5>;



		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  998400000 1>,

			<  960000000 1>,

			< 1094400000 2>,

			< 1248000000 3>,

			< 1344000000 4>,
@@ -712,14 +712,14 @@ 
		qcom,governor-per-policy;



		qcom,cpufreq-table-0 =

			 <  998400 >,

			 <  960000 >,

			 < 1094400 >,

			 < 1248000 >,

			 < 1344000 >,

			 < 1401000 >;



		qcom,cpufreq-table-4 =

			 <  806400 >,

			 <  768000 >,

			 <  902400 >,

			 <  998400 >,

			 < 1094400 >;

drivers/clk/msm/clock-gcc-8952.c

+1 −0
Original line number Diff line number Diff line
@@ -182,6 +182,7 @@ static struct pll_freq_tbl apcs_c0_pll_freq[] = { 
	F_APCS_PLL( 460800000,  24, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL( 499200000,  26, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL( 518400000,  27, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL( 768000000,  40, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL( 806400000,  42, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL( 844800000,  44, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL( 883200000,  46, 0x0, 0x1, 0x0, 0x0, 0x0),