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Commit ae42b9e1 authored by Linus Torvalds's avatar Linus Torvalds
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* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (21 commits)
  Blackfin: define HARDIRQ_BITS again for now
  arch/blackfin: Add kmalloc NULL tests
  Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions
  Blackfin: work around anomaly 05000189
  Blackfin: drop per-cpu loops_per_jiffy tracking
  Blackfin: fix bugs in GPIO resume code
  Blackfin: bf537-stamp: fix irq decl for AD7142
  Blackfin: fix handling of IPEND in interrupt context save
  Blackfin: drop duplicate runtime checking of anomaly 05000448
  Blackfin: fix incomplete renaming of the bfin-twi-lcd driver
  Blackfin: fix wrong CTS inversion
  Blackfin: update handling of anomaly 364 (wrong rev id in BF527-0.1)
  Blackfin: fix early_dma_memcpy() handling of busy channels
  Blackfin: handle BF561 Core B memory regions better when SMP=n
  Blackfin: fix miscompilation in lshrdi3
  Blackfin: fix silent crash when no uClinux MTD filesystem exists
  Blackfin: restore exception banner when dumping crash info
  Blackfin: work around anomaly 05000281
  Blackfin: update anomaly lists to match latest sheets/usage
  Blackfin: drop dead flash_probe call
  ...
parents 6cdbf734 6843f405
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+4 −3
Original line number Original line Diff line number Diff line
@@ -223,9 +223,10 @@
	[--sp] = RETN;
	[--sp] = RETN;
	[--sp] = RETE;
	[--sp] = RETE;
	[--sp] = SEQSTAT;
	[--sp] = SEQSTAT;
#ifdef CONFIG_KGDB
#ifdef CONFIG_DEBUG_KERNEL
	r1.l = lo(IPEND);
	p1.l = lo(IPEND);
	r1.h = hi(IPEND);
	p1.h = hi(IPEND);
	r1 = [p1];
	[--sp] = r1;
	[--sp] = r1;
#else
#else
	[--sp] = r0;	/* Skip IPEND as well. */
	[--sp] = r0;	/* Skip IPEND as well. */
+0 −1
Original line number Original line Diff line number Diff line
@@ -32,7 +32,6 @@ struct blackfin_cpudata {
	struct task_struct *idle;
	struct task_struct *idle;
	unsigned int imemctl;
	unsigned int imemctl;
	unsigned int dmemctl;
	unsigned int dmemctl;
	unsigned long loops_per_jiffy;
	unsigned long dcache_invld_count;
	unsigned long dcache_invld_count;
	unsigned long icache_invld_count;
	unsigned long icache_invld_count;
};
};
+3 −0
Original line number Original line Diff line number Diff line
@@ -6,6 +6,9 @@
extern void ack_bad_irq(unsigned int irq);
extern void ack_bad_irq(unsigned int irq);
#define ack_bad_irq ack_bad_irq
#define ack_bad_irq ack_bad_irq


/* Define until common code gets sane defaults */
#define HARDIRQ_BITS 9

#include <asm-generic/hardirq.h>
#include <asm-generic/hardirq.h>


#endif
#endif
+7 −14
Original line number Original line Diff line number Diff line
@@ -105,23 +105,16 @@ static inline uint32_t __pure bfin_revid(void)
	/* Always use CHIPID, to work around ANOMALY_05000234 */
	/* Always use CHIPID, to work around ANOMALY_05000234 */
	uint32_t revid = (bfin_read_CHIPID() & CHIPID_VERSION) >> 28;
	uint32_t revid = (bfin_read_CHIPID() & CHIPID_VERSION) >> 28;


#ifdef CONFIG_BF52x
#ifdef _BOOTROM_GET_DXE_ADDRESS_TWI
	/* ANOMALY_05000357
	/*
	 * ANOMALY_05000364
	 * Incorrect Revision Number in DSPID Register
	 * Incorrect Revision Number in DSPID Register
	 */
	 */
	if (revid == 0)
	if (ANOMALY_05000364 &&
		switch (bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI)) {
	    bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI) == 0x2796)
		case 0x0010:
			revid = 0;
			break;
		case 0x2796:
		revid = 1;
		revid = 1;
			break;
		default:
			revid = 0xFFFF;
			break;
		}
#endif
#endif

	return revid;
	return revid;
}
}


+14 −15
Original line number Original line Diff line number Diff line
@@ -253,32 +253,31 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
	BUG_ON(src % 4);
	BUG_ON(src % 4);
	BUG_ON(size % 4);
	BUG_ON(size % 4);


	/* Force a sync in case a previous config reset on this channel
	 * occurred.  This is needed so subsequent writes to DMA registers
	 * are not spuriously lost/corrupted.
	 */
	__builtin_bfin_ssync();

	src_ch = 0;
	src_ch = 0;
	/* Find an avalible memDMA channel */
	/* Find an avalible memDMA channel */
	while (1) {
	while (1) {
		if (!src_ch || src_ch == (struct dma_register *)MDMA_S1_NEXT_DESC_PTR) {
		if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) {
			dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
			src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
		} else {
			dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
			dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
			src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
			src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
		} else {
			dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
			src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
		}
		}


		if (!bfin_read16(&src_ch->cfg)) {
		if (!bfin_read16(&src_ch->cfg))
			break;
			break;
		} else {
		else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) {
			if (bfin_read16(&src_ch->irq_status) & DMA_DONE)
			bfin_write16(&src_ch->cfg, 0);
			bfin_write16(&src_ch->cfg, 0);
			break;
		}
		}

	}
	}


	/* Force a sync in case a previous config reset on this channel
	 * occurred.  This is needed so subsequent writes to DMA registers
	 * are not spuriously lost/corrupted.
	 */
	__builtin_bfin_ssync();

	/* Destination */
	/* Destination */
	bfin_write32(&dst_ch->start_addr, dst);
	bfin_write32(&dst_ch->start_addr, dst);
	bfin_write16(&dst_ch->x_count, size >> 2);
	bfin_write16(&dst_ch->x_count, size >> 2);
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