Loading Documentation/devicetree/bindings/arm/msm/acpuclock/clock-a7.txt +1 −1 Original line number Diff line number Diff line Loading @@ -8,7 +8,7 @@ optionally have a register which encodes the maximum rate supported by hw. Required properties: - compatible: "qcom,clock-a7-8226", "qcom,clock-a7-9630", "qcom,clock-a53-8916", "qcom,clock-a7-vpipa", "qcom,clock-a7-9640" "qcom,clock-a7-9640", "qcom,clock-a7-californium" - reg: pairs of physical address and region size - reg-names: "rcg-base" is expected - clock-names: list of names of clock inputs Loading arch/arm/boot/dts/qcom/mdmcalifornium-rumi.dts +22 −0 Original line number Diff line number Diff line Loading @@ -27,3 +27,25 @@ pinctrl-names = "default"; pinctrl-0 = <&uart3_console_active>; }; &clock_gcc { compatible = "qcom,dummycc"; #clock-cells = <1>; }; &clock_cpu { compatible = "qcom,dummycc"; #clock-cells = <1>; }; &clock_debug { status = "disabled"; }; &gdsc_usb30 { compatible = "regulator-fixed"; }; &gdsc_pcie { compatible = "regulator-fixed"; }; arch/arm/boot/dts/qcom/mdmcalifornium.dtsi +37 −12 Original line number Diff line number Diff line Loading @@ -11,9 +11,9 @@ */ #include "skeleton.dtsi" /*TODO: Fixup the correct clock tree */ #include <dt-bindings/clock/msm-clocks-8952.h> #include <dt-bindings/clock/msm-clocks-a7.h> #include <dt-bindings/clock/msm-clocks-californium.h> #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> / { model = "Qualcomm Technologies, Inc. MDM CALIFORNIUM"; Loading Loading @@ -59,6 +59,7 @@ #include "mdmcalifornium-regulator.dtsi" #include "mdmcalifornium-smp2p.dtsi" #include "msm-gdsc.dtsi" &soc { #address-cells = <1>; Loading Loading @@ -102,23 +103,38 @@ }; clock_gcc: qcom,gcc@1800000 { compatible = "qcom,dummycc"; compatible = "qcom,gcc-californium"; reg = <0x1800000 0x80000>; reg-names = "cc_base"; #clock-cells = <1>; }; clock_rpm: qcom,rpmcc@1800000 { compatible = "qcom,dummycc"; #clock-cells = <1>; qcom,regulator-names = "vdd_dig"; vdd_dig-supply = <&pmdcalifornium_s5_level>; }; clock_debug: qcom,cc-debug@1874000 { compatible = "qcom,dummycc"; compatible = "qcom,cc-debug-californium"; reg = <0x1874000 0x4>; reg-names = "cc_base"; #clock-cells = <1>; }; clock_cpu: qcom,cpu-clock-a7@b111050 { compatible = "qcom,dummycc"; clock_cpu: qcom,clock-a7@0b010008 { compatible = "qcom,clock-a7-californium"; reg = <0x0b010008 0x8>; reg-names = "rcg-base"; #clock-cells = <1>; clock-names = "clk-1"; clocks = <&clock_gcc clk_gpll0_ao>; qcom,speed0-bin-v0 = < 0 RPM_SMD_REGULATOR_LEVEL_NONE>, < 400000000 RPM_SMD_REGULATOR_LEVEL_SVS>, < 787200000 RPM_SMD_REGULATOR_LEVEL_NOM>, <1190400000 RPM_SMD_REGULATOR_LEVEL_TURBO>; cpu-vdd-supply = <&pmdcalifornium_s5_level_ao>; }; restart@4ab000 { Loading Loading @@ -216,8 +232,7 @@ compatible = "qcom,msm-lsuart-v14"; reg = <0x78b1000 0x200>; interrupts = <0 109 0>; /*TODO: Fix the clock when tree is available*/ clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; status = "disabled"; Loading Loading @@ -416,3 +431,13 @@ qcom,fragmented-data; }; }; &gdsc_usb30 { reg = <0x185e078 0x4>; status = "ok"; }; &gdsc_pcie { reg = <0x0185d044 0x4>; status = "ok"; }; drivers/clk/msm/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -21,6 +21,7 @@ obj-$(CONFIG_ARCH_MDMCALIFORNIUM) += clock-gcc-californium.o # ACPU clock obj-$(CONFIG_ARCH_MDM9640) += clock-a7.o obj-$(CONFIG_ARCH_MDMCALIFORNIUM) += clock-a7.o obj-$(CONFIG_ARCH_MSM8916) += clock-a7.o obj-$(CONFIG_ARCH_MSM8916) += clock-cpu-8939.o obj-$(CONFIG_ARCH_MSM8916) += clock-gcc-8952.o Loading drivers/clk/msm/clock-a7.c +1 −0 Original line number Diff line number Diff line Loading @@ -470,6 +470,7 @@ static struct of_device_id clock_a7_match_table[] = { {.compatible = "qcom,clock-a7-9630"}, {.compatible = "qcom,clock-a7-9640"}, {.compatible = "qcom,clock-a53-8916"}, {.compatible = "qcom,clock-a7-californium"}, {} }; Loading Loading
Documentation/devicetree/bindings/arm/msm/acpuclock/clock-a7.txt +1 −1 Original line number Diff line number Diff line Loading @@ -8,7 +8,7 @@ optionally have a register which encodes the maximum rate supported by hw. Required properties: - compatible: "qcom,clock-a7-8226", "qcom,clock-a7-9630", "qcom,clock-a53-8916", "qcom,clock-a7-vpipa", "qcom,clock-a7-9640" "qcom,clock-a7-9640", "qcom,clock-a7-californium" - reg: pairs of physical address and region size - reg-names: "rcg-base" is expected - clock-names: list of names of clock inputs Loading
arch/arm/boot/dts/qcom/mdmcalifornium-rumi.dts +22 −0 Original line number Diff line number Diff line Loading @@ -27,3 +27,25 @@ pinctrl-names = "default"; pinctrl-0 = <&uart3_console_active>; }; &clock_gcc { compatible = "qcom,dummycc"; #clock-cells = <1>; }; &clock_cpu { compatible = "qcom,dummycc"; #clock-cells = <1>; }; &clock_debug { status = "disabled"; }; &gdsc_usb30 { compatible = "regulator-fixed"; }; &gdsc_pcie { compatible = "regulator-fixed"; };
arch/arm/boot/dts/qcom/mdmcalifornium.dtsi +37 −12 Original line number Diff line number Diff line Loading @@ -11,9 +11,9 @@ */ #include "skeleton.dtsi" /*TODO: Fixup the correct clock tree */ #include <dt-bindings/clock/msm-clocks-8952.h> #include <dt-bindings/clock/msm-clocks-a7.h> #include <dt-bindings/clock/msm-clocks-californium.h> #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> / { model = "Qualcomm Technologies, Inc. MDM CALIFORNIUM"; Loading Loading @@ -59,6 +59,7 @@ #include "mdmcalifornium-regulator.dtsi" #include "mdmcalifornium-smp2p.dtsi" #include "msm-gdsc.dtsi" &soc { #address-cells = <1>; Loading Loading @@ -102,23 +103,38 @@ }; clock_gcc: qcom,gcc@1800000 { compatible = "qcom,dummycc"; compatible = "qcom,gcc-californium"; reg = <0x1800000 0x80000>; reg-names = "cc_base"; #clock-cells = <1>; }; clock_rpm: qcom,rpmcc@1800000 { compatible = "qcom,dummycc"; #clock-cells = <1>; qcom,regulator-names = "vdd_dig"; vdd_dig-supply = <&pmdcalifornium_s5_level>; }; clock_debug: qcom,cc-debug@1874000 { compatible = "qcom,dummycc"; compatible = "qcom,cc-debug-californium"; reg = <0x1874000 0x4>; reg-names = "cc_base"; #clock-cells = <1>; }; clock_cpu: qcom,cpu-clock-a7@b111050 { compatible = "qcom,dummycc"; clock_cpu: qcom,clock-a7@0b010008 { compatible = "qcom,clock-a7-californium"; reg = <0x0b010008 0x8>; reg-names = "rcg-base"; #clock-cells = <1>; clock-names = "clk-1"; clocks = <&clock_gcc clk_gpll0_ao>; qcom,speed0-bin-v0 = < 0 RPM_SMD_REGULATOR_LEVEL_NONE>, < 400000000 RPM_SMD_REGULATOR_LEVEL_SVS>, < 787200000 RPM_SMD_REGULATOR_LEVEL_NOM>, <1190400000 RPM_SMD_REGULATOR_LEVEL_TURBO>; cpu-vdd-supply = <&pmdcalifornium_s5_level_ao>; }; restart@4ab000 { Loading Loading @@ -216,8 +232,7 @@ compatible = "qcom,msm-lsuart-v14"; reg = <0x78b1000 0x200>; interrupts = <0 109 0>; /*TODO: Fix the clock when tree is available*/ clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; status = "disabled"; Loading Loading @@ -416,3 +431,13 @@ qcom,fragmented-data; }; }; &gdsc_usb30 { reg = <0x185e078 0x4>; status = "ok"; }; &gdsc_pcie { reg = <0x0185d044 0x4>; status = "ok"; };
drivers/clk/msm/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -21,6 +21,7 @@ obj-$(CONFIG_ARCH_MDMCALIFORNIUM) += clock-gcc-californium.o # ACPU clock obj-$(CONFIG_ARCH_MDM9640) += clock-a7.o obj-$(CONFIG_ARCH_MDMCALIFORNIUM) += clock-a7.o obj-$(CONFIG_ARCH_MSM8916) += clock-a7.o obj-$(CONFIG_ARCH_MSM8916) += clock-cpu-8939.o obj-$(CONFIG_ARCH_MSM8916) += clock-gcc-8952.o Loading
drivers/clk/msm/clock-a7.c +1 −0 Original line number Diff line number Diff line Loading @@ -470,6 +470,7 @@ static struct of_device_id clock_a7_match_table[] = { {.compatible = "qcom,clock-a7-9630"}, {.compatible = "qcom,clock-a7-9640"}, {.compatible = "qcom,clock-a53-8916"}, {.compatible = "qcom,clock-a7-californium"}, {} }; Loading