Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit adb55155 authored by Sunil Khatri's avatar Sunil Khatri Committed by Gerrit - the friendly Code Review server
Browse files

msm: kgsl: Disable RB sampler data path optimization 



Disable RB sampler data path DP2 clock gating optimization
for 1-SP A5XX GPU's. Optimization leads to precision
difference during interpolation which cause rendering
difference between Binning and Direct rendering mode.

Change-Id: I40d1ce2f5db0ed75453feda5c31152f8201b8697
Signed-off-by: default avatarSunil Khatri <sunilkh@codeaurora.org>
parent f66ce13e

Documentation/devicetree/bindings/gpu/adreno.txt

+2 −0
Original line number Diff line number Diff line
@@ -157,6 +157,8 @@ GPU Quirks: 
- qcom,gpu-quirk-fault-detect-mask:

				Mask out RB1-3 activity signals from HW hang

				detection logic

- qcom,gpu-quirk-dp2clockgating-disable:

				Disable RB sampler data path clock gating optimization



The following properties are optional as collecting data via coresight might

not be supported for every chipset. The documentation for coresight

drivers/gpu/msm/a5xx_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -561,6 +561,7 @@ 




/* RB registers */

#define A5XX_RB_DBG_ECO_CNT                 0xCC4

#define A5XX_RB_ADDR_MODE_CNTL              0xCC5

#define A5XX_RB_MODE_CNTL                   0xCC6

#define A5XX_RB_PERFCTR_RB_SEL_0            0xCD0

drivers/gpu/msm/adreno.c

+2 −0
Original line number Diff line number Diff line
@@ -826,6 +826,8 @@ static struct { 
	 { ADRENO_QUIRK_IOMMU_SYNC, "qcom,gpu-quirk-iommu-sync" },

	 { ADRENO_QUIRK_CRITICAL_PACKETS, "qcom,gpu-quirk-critical-packets" },

	 { ADRENO_QUIRK_FAULT_DETECT_MASK, "qcom,gpu-quirk-fault-detect-mask" },

	 { ADRENO_QUIRK_DISABLE_RB_DP2CLOCKGATING,

			"qcom,gpu-quirk-dp2clockgating-disable" },

};



static int adreno_of_get_power(struct adreno_device *adreno_dev,

drivers/gpu/msm/adreno.h

+2 −0
Original line number Diff line number Diff line
@@ -121,6 +121,8 @@ 
#define ADRENO_QUIRK_CRITICAL_PACKETS BIT(2)

/* Mask out RB1-3 activity signals from HW hang detection logic */

#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(3)

/* Disable RB sampler datapath clock gating optimization */

#define ADRENO_QUIRK_DISABLE_RB_DP2CLOCKGATING BIT(4)



/* Flags to control command packet settings */

#define KGSL_CMD_FLAGS_NONE             0

drivers/gpu/msm/adreno_a5xx.c

+7 −0
Original line number Diff line number Diff line
@@ -1935,6 +1935,13 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
			kgsl_regrmw(device, A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));

	}



	if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_DISABLE_RB_DP2CLOCKGATING)) {

		/*

		 * Disable RB sampler datapath DP2 clock gating

		 * optimization for 1-SP GPU's, by default it is enabled.

		 */

		kgsl_regrmw(device, A5XX_RB_DBG_ECO_CNT, 0, (1 << 9));

	}

	/* Set the USE_RETENTION_FLOPS chicken bit */

	kgsl_regwrite(device, A5XX_CP_CHICKEN_DBG, 0x02000000);