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Commit ad8e4b71 authored by Phani Kumar Uppalapati's avatar Phani Kumar Uppalapati Committed by Gerrit - the friendly Code Review server
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ASoC: wcd9335: Update AFE codec register config table 



WCD9335 codec register configuration needs to be
sent to Audio Front End (AFE) module within Q6 DSP
so as to access codec registers to support features
like speaker protection and active noise cancellation.
Update the codec register config table that needs to
be sent to AFE.

Change-Id: I37af4ea3ea7c942cea857bc15541b55e5bf81d0b
Signed-off-by: default avatarPhani Kumar Uppalapati <phaniu@codeaurora.org>
parent 81281f53

sound/soc/codecs/wcd9335.c

+92 −2
Original line number Diff line number Diff line
@@ -87,6 +87,7 @@ 


#define CPE_FLL_CLK_75MHZ 75000000

#define CPE_FLL_CLK_150MHZ 150000000

#define WCD9335_REG_BITS 8



static int cpe_debug_mode = 1;

module_param(cpe_debug_mode, int,
@@ -103,6 +104,93 @@ static struct afe_param_slimbus_slave_port_cfg tasha_slimbus_slave_port_cfg = { 
	.num_channels = 1

};



static struct afe_param_cdc_reg_page_cfg tasha_cdc_reg_page_cfg = {

	.minor_version = AFE_API_VERSION_CDC_REG_PAGE_CFG,

	.enable = 1,

	.proc_id = AFE_CDC_REG_PAGE_ASSIGN_PROC_ID_1,

};



static struct afe_param_cdc_reg_cfg audio_reg_cfg[] = {

	{

		1,

		(TASHA_REGISTER_START_OFFSET + WCD9335_SOC_MAD_MAIN_CTL_1),

		HW_MAD_AUDIO_ENABLE, 0x1, WCD9335_REG_BITS, 0

	},

	{

		1,

		(TASHA_REGISTER_START_OFFSET + WCD9335_SOC_MAD_AUDIO_CTL_3),

		HW_MAD_AUDIO_SLEEP_TIME, 0xF, WCD9335_REG_BITS, 0

	},

	{

		1,

		(TASHA_REGISTER_START_OFFSET + WCD9335_SOC_MAD_AUDIO_CTL_4),

		HW_MAD_TX_AUDIO_SWITCH_OFF, 0x1, WCD9335_REG_BITS, 0

	},

	{

		1,

		(TASHA_REGISTER_START_OFFSET + WCD9335_INTR_CFG),

		MAD_AUDIO_INT_DEST_SELECT_REG, 0x2, WCD9335_REG_BITS, 0

	},

	{

		1,

		(TASHA_REGISTER_START_OFFSET + WCD9335_INTR_PIN2_MASK3),

		MAD_AUDIO_INT_MASK_REG, 0x1, WCD9335_REG_BITS, 0

	},

	{

		1,

		(TASHA_REGISTER_START_OFFSET + WCD9335_INTR_PIN2_STATUS3),

		MAD_AUDIO_INT_STATUS_REG, 0x1, WCD9335_REG_BITS, 0

	},

	{

		1,

		(TASHA_REGISTER_START_OFFSET + WCD9335_INTR_PIN2_CLEAR3),

		MAD_AUDIO_INT_CLEAR_REG, 0x1, WCD9335_REG_BITS, 0

	},

	{

		1,

		(TASHA_REGISTER_START_OFFSET + TASHA_SB_PGD_PORT_TX_BASE),

		SB_PGD_PORT_TX_WATERMARK_N, 0x1E, WCD9335_REG_BITS, 0x1

	},

	{

		1,

		(TASHA_REGISTER_START_OFFSET + TASHA_SB_PGD_PORT_TX_BASE),

		SB_PGD_PORT_TX_ENABLE_N, 0x1, WCD9335_REG_BITS, 0x1

	},

	{

		1,

		(TASHA_REGISTER_START_OFFSET + TASHA_SB_PGD_PORT_RX_BASE),

		SB_PGD_PORT_RX_WATERMARK_N, 0x1E, WCD9335_REG_BITS, 0x1

	},

	{

		1,

		(TASHA_REGISTER_START_OFFSET + TASHA_SB_PGD_PORT_RX_BASE),

		SB_PGD_PORT_RX_ENABLE_N, 0x1, WCD9335_REG_BITS, 0x1

	},

	{	1,

		(TASHA_REGISTER_START_OFFSET + WCD9335_CDC_ANC0_IIR_ADAPT_CTL),

		AANC_FF_GAIN_ADAPTIVE, 0x4, WCD9335_REG_BITS, 0

	},

	{	1,

		(TASHA_REGISTER_START_OFFSET + WCD9335_CDC_ANC0_IIR_ADAPT_CTL),

		AANC_FFGAIN_ADAPTIVE_EN, 0x8, WCD9335_REG_BITS, 0

	},

	{

		1,

		(TASHA_REGISTER_START_OFFSET + WCD9335_CDC_ANC0_FF_A_GAIN_CTL),

		AANC_GAIN_CONTROL, 0xFF, WCD9335_REG_BITS, 0

	},

};



static struct afe_param_cdc_reg_cfg_data tasha_audio_reg_cfg = {

	.num_registers = ARRAY_SIZE(audio_reg_cfg),

	.reg_data = audio_reg_cfg,

};



static struct afe_param_id_cdc_aanc_version tasha_cdc_aanc_version = {

	.cdc_aanc_minor_version = AFE_API_VERSION_CDC_AANC_VERSION,

	.aanc_hw_version        = AANC_HW_BLOCK_VERSION_2,

};



enum {

	VI_SENSE_1,

	VI_SENSE_2,
@@ -487,15 +575,17 @@ void *tasha_get_afe_config(struct snd_soc_codec *codec, 
	case AFE_SLIMBUS_SLAVE_CONFIG:

		return &priv->slimbus_slave_cfg;

	case AFE_CDC_REGISTERS_CONFIG:

		return NULL;

		return &tasha_audio_reg_cfg;

	case AFE_SLIMBUS_SLAVE_PORT_CONFIG:

		return &tasha_slimbus_slave_port_cfg;

	case AFE_AANC_VERSION:

		return NULL;

		return &tasha_cdc_aanc_version;

	case AFE_CLIP_BANK_SEL:

		return NULL;

	case AFE_CDC_CLIP_REGISTERS_CONFIG:

		return NULL;

	case AFE_CDC_REGISTER_PAGE_CONFIG:

		return &tasha_cdc_reg_page_cfg;

	default:

		dev_err(codec->dev, "%s: Unknown config_type 0x%x\n",

			__func__, config_type);

sound/soc/codecs/wcd9xxx-common-v2.h

+74 −0
Original line number Diff line number Diff line
@@ -132,4 +132,78 @@ extern void wcd_clsh_fsm(struct snd_soc_codec *codec, 


extern void wcd_clsh_init(struct wcd_clsh_cdc_data *clsh);



enum {

	RESERVED = 0,

	AANC_LPF_FF_FB = 1,

	AANC_LPF_COEFF_MSB,

	AANC_LPF_COEFF_LSB,

	HW_MAD_AUDIO_ENABLE,

	HW_MAD_ULTR_ENABLE,

	HW_MAD_BEACON_ENABLE,

	HW_MAD_AUDIO_SLEEP_TIME,

	HW_MAD_ULTR_SLEEP_TIME,

	HW_MAD_BEACON_SLEEP_TIME,

	HW_MAD_TX_AUDIO_SWITCH_OFF,

	HW_MAD_TX_ULTR_SWITCH_OFF,

	HW_MAD_TX_BEACON_SWITCH_OFF,

	MAD_AUDIO_INT_DEST_SELECT_REG,

	MAD_ULT_INT_DEST_SELECT_REG,

	MAD_BEACON_INT_DEST_SELECT_REG,

	MAD_CLIP_INT_DEST_SELECT_REG,

	MAD_VBAT_INT_DEST_SELECT_REG,

	MAD_AUDIO_INT_MASK_REG,

	MAD_ULT_INT_MASK_REG,

	MAD_BEACON_INT_MASK_REG,

	MAD_CLIP_INT_MASK_REG,

	MAD_VBAT_INT_MASK_REG,

	MAD_AUDIO_INT_STATUS_REG,

	MAD_ULT_INT_STATUS_REG,

	MAD_BEACON_INT_STATUS_REG,

	MAD_CLIP_INT_STATUS_REG,

	MAD_VBAT_INT_STATUS_REG,

	MAD_AUDIO_INT_CLEAR_REG,

	MAD_ULT_INT_CLEAR_REG,

	MAD_BEACON_INT_CLEAR_REG,

	MAD_CLIP_INT_CLEAR_REG,

	MAD_VBAT_INT_CLEAR_REG,

	SB_PGD_PORT_TX_WATERMARK_N,

	SB_PGD_PORT_TX_ENABLE_N,

	SB_PGD_PORT_RX_WATERMARK_N,

	SB_PGD_PORT_RX_ENABLE_N,

	SB_PGD_TX_PORTn_MULTI_CHNL_0,

	SB_PGD_TX_PORTn_MULTI_CHNL_1,

	SB_PGD_RX_PORTn_MULTI_CHNL_0,

	SB_PGD_RX_PORTn_MULTI_CHNL_1,

	AANC_FF_GAIN_ADAPTIVE,

	AANC_FFGAIN_ADAPTIVE_EN,

	AANC_GAIN_CONTROL,

	SPKR_CLIP_PIPE_BANK_SEL,

	SPKR_CLIPDET_VAL0,

	SPKR_CLIPDET_VAL1,

	SPKR_CLIPDET_VAL2,

	SPKR_CLIPDET_VAL3,

	SPKR_CLIPDET_VAL4,

	SPKR_CLIPDET_VAL5,

	SPKR_CLIPDET_VAL6,

	SPKR_CLIPDET_VAL7,

	VBAT_RELEASE_INT_DEST_SELECT_REG,

	VBAT_RELEASE_INT_MASK_REG,

	VBAT_RELEASE_INT_STATUS_REG,

	VBAT_RELEASE_INT_CLEAR_REG,

	MAD2_CLIP_INT_DEST_SELECT_REG,

	MAD2_CLIP_INT_MASK_REG,

	MAD2_CLIP_INT_STATUS_REG,

	MAD2_CLIP_INT_CLEAR_REG,

	SPKR2_CLIP_PIPE_BANK_SEL,

	SPKR2_CLIPDET_VAL0,

	SPKR2_CLIPDET_VAL1,

	SPKR2_CLIPDET_VAL2,

	SPKR2_CLIPDET_VAL3,

	SPKR2_CLIPDET_VAL4,

	SPKR2_CLIPDET_VAL5,

	SPKR2_CLIPDET_VAL6,

	SPKR2_CLIPDET_VAL7,

	MAX_CFG_REGISTERS,

};



#endif