Merge branch 'mdm9640_base' into 'msm-3.18'

Introduction

=============

The power management integrated circuit (PMIC) records the reason the

Application processor was powered on in Shared Memory.

The hardware and software used is the shared memory interface. This document

is not for the purpose of describing this interface, but to identify the

possible values for this data item.

Description

===========

Shared memory item (SMEM_POWER_ON_STATUS_INFO) is read to get access to

this data. The table below identifies the possible values stored.

power_on_status values set by the PMIC for power on event:

----------------------------------------------------------

0x01 -- keyboard power on

0x02 -- RTC alarm

0x04 -- cable power on

0x08 -- SMPL

0x10 -- Watch Dog timeout

0x20 -- USB charger

0x40 -- Wall charger

0xFF -- error reading power_on_status value

* Qualcomm Application CPU clock driver

clock-a7 is the driver for the Root Clock Generator (rcg) hw which controls

the cpu rate. RCGs support selecting one of several clock inputs, as well as

a configurable divider. This hw is different than normal rcgs in that it may

optionally have a register which encodes the maximum rate supported by hw.

Required properties:

- compatible: "qcom,clock-a7-8226", "qcom,clock-a7-9630",

		"qcom,clock-a53-8916", "qcom,clock-a7-vpipa",

		"qcom,clock-a7-9640"

- reg: pairs of physical address and region size

- reg-names: "rcg-base" is expected

- clock-names: list of names of clock inputs

- qcom,speedX-bin-vZ:

		A table of CPU frequency (Hz) to regulator voltage (uV) mapping.

		Format: <freq uV>

		This represents the max frequency possible for each possible

		power configuration for a CPU that's binned as speed bin X,

		speed bin revision Z. Speed bin values can be between [0-7]

		and the version can be between [0-3].

- cpu-vdd-supply: regulator phandle for cpu power domain.

Optional properties:

- reg-names: "efuse", "efuse1"

- qcom,safe-freq: Frequency in HZ

	     When switching rates from A to B, the mux div clock will

             instead switch from A -> safe_freq -> B.

- qcom,enable-opp: This will allow to register the cpu clock with OPP

	     framework.

Example:

	qcom,acpuclk@f9011050 {

                compatible = "qcom,clock-a7-8226";

                reg = <0xf9011050 0x8>;

                reg-names = "rcg_base";

                cpu-vdd-supply = <&apc_vreg_corner>;

                clock-names = "clk-4", "clk-5";

		qcom,speed0-bin-v0 =

			<384000000 1150000>,

			<600000000 1200000>;

        };

MSM Pinctrl Bindings

Required properties:

- compatible: "qcom,msm8996-pinctrl"

	       "qcom,mdm9640-pinctrl"

- reg: Should be the base address and length of the TLMM block.

- interrupts: Should be the parent IRQ of the TLMM block.

- interrupt-controller: Marks the device node as an interrupt controller.

- #interrupt-cells: Should be two.

- gpio-controller: Marks the device node as a GPIO controller.

- #gpio-cells : Should be two.

                The first cell is the gpio pin number and the

                second cell is used for optional parameters.

config ARCH_MSM

config ARCH_MSM

	bool "Qualcomm MSM (non-multiplatform)"

	bool "Qualcomm MSM (non-multiplatform)"

	select ARCH_REQUIRE_GPIOLIB

	select ARCH_REQUIRE_GPIOLIB

	select CLKDEV_LOOKUP

	select GENERIC_CLOCKEVENTS

	select GENERIC_CLOCKEVENTS

	select GENERIC_ALLOCATOR

	select HAVE_CLK

	select HAVE_CLK_PREPARE

	select SOC_BUS

	select SOC_BUS

	select MULTI_IRQ_HANDLER

	select SPARSE_IRQ

	select USE_OF

	help

	help

	  Support for Qualcomm MSM/QSD based systems.  This runs on the

	  Support for Qualcomm MSM/QSD based systems.  This runs on the

	  apps processor of the MSM/QSD and depends on a shared memory

	  apps processor of the MSM/QSD and depends on a shared memory

	  0xf8000000. This assumes the zImage being placed in the first 128MB

	  0xf8000000. This assumes the zImage being placed in the first 128MB

	  from start of memory.

	  from start of memory.

config ARM_DECOMPRESSOR_LIMIT

	hex "Limit the decompressor memory area"

	default 0x10000000

	help

	  Allows overriding of the memory size that decompressor maps with

	  read, write and execute permissions to avoid speculative prefetch.

	  By default ARM_DECOMPRESSOR_LIMIT maps first 1GB of memory

	  with read, write and execute permissions and reset of the memory

	  as strongly ordered.

endmenu

endmenu

menu "CPU Power Management"

menu "CPU Power Management"

	      8 - SIGSEGV faults

	      8 - SIGSEGV faults

	     16 - SIGBUS faults

	     16 - SIGBUS faults

config KERNEL_TEXT_RDONLY

	bool "Set kernel text section pages as read only"

	depends on FREE_PAGES_RDONLY

	help

	  The kernel text pages are always mapped in the kernel.

	  This means that anyone can write to the page if they have

	  the address. Enable this option to mark the kernel text pages

	  as read only to trigger a fault if any code attempts to write

	  to a page part of the kernel text section. This may have a

	  performance impact.

	  If unsure, say N.

# These options are only for real kernel hackers who want to get their hands dirty.

# These options are only for real kernel hackers who want to get their hands dirty.

config DEBUG_LL

config DEBUG_LL

	bool "Kernel low-level debugging functions (read help!)"

	bool "Kernel low-level debugging functions (read help!)"