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Commit acedba5c authored by Ingrid Gallardo's avatar Ingrid Gallardo Committed by Gerrit - the friendly Code Review server
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msm: mdss: update vbif remapper for sde 3.0 



Starting with sde 3.0, vbif remapper registers
have changed. Update programming sequence
to configure vbif remapper registers accordingly.

Change-Id: I7cfac789576300f421de076ac9abca9b85c6168d
Signed-off-by: default avatarIngrid Gallardo <ingridg@codeaurora.org>
parent ba08b758

drivers/video/msm/mdss/mdss.h

+1 −0
Original line number Diff line number Diff line
@@ -190,6 +190,7 @@ enum mdss_qos_settings { 
	MDSS_QOS_SIMPLIFIED_PREFILL,

	MDSS_QOS_VBLANK_PANIC_CTRL,

	MDSS_QOS_TS_PREFILL,

	MDSS_QOS_REMAPPER,

	MDSS_QOS_MAX,

};

drivers/video/msm/mdss/mdss_mdp.c

+1 −0
Original line number Diff line number Diff line
@@ -1531,6 +1531,7 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) 
		mdata->rects_per_sspp[MDSS_MDP_PIPE_TYPE_DMA] = 2;



		set_bit(MDSS_QOS_PER_PIPE_IB, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_TS_PREFILL, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_OVERHEAD_FACTOR, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_CDP, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_OTLIM, mdata->mdss_qos_map);

drivers/video/msm/mdss/mdss_mdp_hwio.h

+3 −0
Original line number Diff line number Diff line
@@ -812,6 +812,9 @@ enum mdss_mdp_pingpong_index { 
#define MDSS_VBIF_QOS_REMAP_BASE	0x020

#define MDSS_VBIF_QOS_REMAP_ENTRIES	0x4



#define MDSS_VBIF_QOS_RP_REMAP_BASE	0x550

#define MDSS_VBIF_QOS_LVL_REMAP_BASE	0x570



#define MDSS_VBIF_FIXED_SORT_EN	0x30

#define MDSS_VBIF_FIXED_SORT_SEL0	0x34

drivers/video/msm/mdss/mdss_mdp_pipe.c

+47 −13
Original line number Diff line number Diff line
@@ -1005,26 +1005,60 @@ int mdss_mdp_pipe_map(struct mdss_mdp_pipe *pipe) 
static void mdss_mdp_qos_vbif_remapper_setup(struct mdss_data_type *mdata,

			struct mdss_mdp_pipe *pipe, bool is_realtime)

{

	u32 mask, reg_val, i, vbif_qos;

	u32 mask, reg_val, reg_val_lvl, i, vbif_qos;

	u32 reg_high;

	bool is_nrt_vbif = mdss_mdp_is_nrt_vbif_client(mdata, pipe);



	if (mdata->npriority_lvl == 0)

		return;



	if (test_bit(MDSS_QOS_REMAPPER, mdata->mdss_qos_map)) {

		mutex_lock(&mdata->reg_lock);

		for (i = 0; i < mdata->npriority_lvl; i++) {

		reg_val = MDSS_VBIF_READ(mdata, MDSS_VBIF_QOS_REMAP_BASE + i*4,

			reg_high = ((pipe->xin_id & 0x8) >> 3) * 4 + (i * 8);



			reg_val = MDSS_VBIF_READ(mdata,

				MDSS_VBIF_QOS_RP_REMAP_BASE +

				reg_high, is_nrt_vbif);

			reg_val_lvl = MDSS_VBIF_READ(mdata,

				MDSS_VBIF_QOS_LVL_REMAP_BASE + reg_high,

				is_nrt_vbif);



			mask = 0x3 << (pipe->xin_id * 4);

			vbif_qos = is_realtime ?

				mdata->vbif_rt_qos[i] : mdata->vbif_nrt_qos[i];



			reg_val &= ~(mask);

			reg_val |= vbif_qos << (pipe->xin_id * 4);



			reg_val_lvl &= ~(mask);

			reg_val_lvl |= vbif_qos << (pipe->xin_id * 4);



			pr_debug("idx:%d xin:%d reg:0x%x val:0x%x lvl:0x%x\n",

			   i, pipe->xin_id, reg_high, reg_val, reg_val_lvl);

			MDSS_VBIF_WRITE(mdata, MDSS_VBIF_QOS_RP_REMAP_BASE +

				reg_high, reg_val, is_nrt_vbif);

			MDSS_VBIF_WRITE(mdata, MDSS_VBIF_QOS_LVL_REMAP_BASE +

				reg_high, reg_val_lvl, is_nrt_vbif);

		}

		mutex_unlock(&mdata->reg_lock);

	} else {

		mutex_lock(&mdata->reg_lock);

		for (i = 0; i < mdata->npriority_lvl; i++) {

			reg_val = MDSS_VBIF_READ(mdata,

				MDSS_VBIF_QOS_REMAP_BASE + i*4, is_nrt_vbif);



			mask = 0x3 << (pipe->xin_id * 2);

			reg_val &= ~(mask);

			vbif_qos = is_realtime ?

				mdata->vbif_rt_qos[i] : mdata->vbif_nrt_qos[i];

			reg_val |= vbif_qos << (pipe->xin_id * 2);

		MDSS_VBIF_WRITE(mdata, MDSS_VBIF_QOS_REMAP_BASE + i*4, reg_val,

								is_nrt_vbif);

			MDSS_VBIF_WRITE(mdata, MDSS_VBIF_QOS_REMAP_BASE + i*4,

				reg_val, is_nrt_vbif);

		}

		mutex_unlock(&mdata->reg_lock);

	}

}



/**

 * mdss_mdp_fixed_qos_arbiter_setup - Program the RT/NRT registers based on