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Commit ace4b3fd authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

sh/PCI: Pass GAPSPCI_DMA_BASE CPU & bus address to dma_declare_coherent_memory() 



dma_declare_coherent_memory() needs both the CPU physical address and the
bus address of the device memory.  They are the same on this platform, but
in general we should use pcibios_resource_to_bus() to account for any
address translation done by the PCI host bridge.

This makes no difference on Dreamcast, but is safer if the usage is copied
to future drivers.

Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
CC: Magnus Damm <damm@opensource.se>
CC: linux-sh@vger.kernel.org
parent 88a984ba

arch/sh/drivers/pci/fixups-dreamcast.c

+15 −3
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ 
static void gapspci_fixup_resources(struct pci_dev *dev)

{

	struct pci_channel *p = dev->sysdata;

	struct resource res;

	struct pci_bus_region region;



	printk(KERN_NOTICE "PCI: Fixing up device %s\n", pci_name(dev));
@@ -50,11 +52,21 @@ static void gapspci_fixup_resources(struct pci_dev *dev) 


		/*

		 * Redirect dma memory allocations to special memory window.

		 *

		 * If this GAPSPCI region were mapped by a BAR, the CPU

		 * phys_addr_t would be pci_resource_start(), and the bus

		 * address would be pci_bus_address(pci_resource_start()).

		 * But apparently there's no BAR mapping it, so we just

		 * "know" its CPU address is GAPSPCI_DMA_BASE.

		 */

		res.start = GAPSPCI_DMA_BASE;

		res.end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1;

		res.flags = IORESOURCE_MEM;

		pcibios_resource_to_bus(dev->bus, &region, &res);

		BUG_ON(!dma_declare_coherent_memory(&dev->dev,

						GAPSPCI_DMA_BASE,

						GAPSPCI_DMA_BASE,

						GAPSPCI_DMA_SIZE,

						res.start,

						region.start,

						resource_size(&res),

						DMA_MEMORY_MAP |

						DMA_MEMORY_EXCLUSIVE));

		break;