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Commit acc66b57 authored by Skylar Chang's avatar Skylar Chang
Browse files

msm: ipa: apply reset wa to GPI channels 



When resetting a GSI channel a special handling is needed
if there is an open aggregation frame. This handling is applied
to USB and MHI channels. This commit applies this handling to
GPI (system) channels as well.

Change-Id: Iebdf3d7375a4bd584c75503f01e64d7106f25e5a
CRs-Fixed: 2029089
Acked-by: default avatarAdy Abraham <adya@qti.qualcomm.com>
Signed-off-by: default avatarSkylar Chang <chiaweic@codeaurora.org>
parent 75ab77d4

drivers/platform/msm/ipa/ipa_v3/ipa_client.c

+24 −0
Original line number Diff line number Diff line
@@ -857,6 +857,8 @@ static int ipa3_reset_with_open_aggr_frame_wa(u32 clnt_hdl, 
	struct gsi_xfer_elem xfer_elem;

	int i;

	int aggr_active_bitmap = 0;

	bool pipe_suspended = false;

	struct ipa_ep_cfg_ctrl ctrl;



	IPADBG("Applying reset channel with open aggregation frame WA\n");

	ipahal_write_reg(IPA_AGGR_FORCE_CLOSE, (1 << clnt_hdl));
@@ -883,6 +885,15 @@ static int ipa3_reset_with_open_aggr_frame_wa(u32 clnt_hdl, 
	if (result)

		return -EFAULT;



	ipahal_read_reg_n_fields(IPA_ENDP_INIT_CTRL_n, clnt_hdl, &ctrl);

	if (ctrl.ipa_ep_suspend) {

		IPADBG("pipe is suspended, remove suspend\n");

		pipe_suspended = true;

		ctrl.ipa_ep_suspend = false;

		ipahal_write_reg_n_fields(IPA_ENDP_INIT_CTRL_n,

			clnt_hdl, &ctrl);

	}



	/* Start channel and put 1 Byte descriptor on it */

	gsi_res = gsi_start_channel(ep->gsi_chan_hdl);

	if (gsi_res != GSI_STATUS_SUCCESS) {
@@ -942,6 +953,13 @@ static int ipa3_reset_with_open_aggr_frame_wa(u32 clnt_hdl, 
	 */

	msleep(IPA_POLL_AGGR_STATE_SLEEP_MSEC);



	if (pipe_suspended) {

		IPADBG("suspend the pipe again\n");

		ctrl.ipa_ep_suspend = true;

		ipahal_write_reg_n_fields(IPA_ENDP_INIT_CTRL_n,

			clnt_hdl, &ctrl);

	}



	/* Restore channels properties */

	result = ipa3_restore_channel_properties(ep, &orig_chan_props,

		&orig_chan_scratch);
@@ -956,6 +974,12 @@ queue_xfer_fail: 
	ipa3_stop_gsi_channel(clnt_hdl);

	dma_free_coherent(ipa3_ctx->pdev, 1, buff, dma_addr);

start_chan_fail:

	if (pipe_suspended) {

		IPADBG("suspend the pipe again\n");

		ctrl.ipa_ep_suspend = true;

		ipahal_write_reg_n_fields(IPA_ENDP_INIT_CTRL_n,

			clnt_hdl, &ctrl);

	}

	ipa3_restore_channel_properties(ep, &orig_chan_props,

		&orig_chan_scratch);

restore_props_fail:

drivers/platform/msm/ipa/ipa_v3/ipa_dp.c

+1 −1
Original line number Diff line number Diff line
@@ -1420,7 +1420,7 @@ int ipa3_teardown_sys_pipe(u32 clnt_hdl) 
			BUG();

			return result;

		}

		result = gsi_reset_channel(ep->gsi_chan_hdl);

		result = ipa3_reset_gsi_channel(clnt_hdl);

		if (result != GSI_STATUS_SUCCESS) {

			IPAERR("Failed to reset chan: %d.\n", result);

			BUG();

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c

+17 −1
Original line number Diff line number Diff line
@@ -645,6 +645,21 @@ static void ipareg_construct_endp_init_ctrl_n(enum ipahal_reg_name reg, 
		IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_BMSK);

}



static void ipareg_parse_endp_init_ctrl_n(enum ipahal_reg_name reg,

	void *fields, u32 val)

{

	struct ipa_ep_cfg_ctrl *ep_ctrl =

		(struct ipa_ep_cfg_ctrl *)fields;



	ep_ctrl->ipa_ep_suspend =

		((val & IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_BMSK) >>

			IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_SHFT);



	ep_ctrl->ipa_ep_delay =

		((val & IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_BMSK) >>

		IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_SHFT);

}



static void ipareg_construct_endp_init_nat_n(enum ipahal_reg_name reg,

		const void *fields, u32 *val)

{
@@ -1044,7 +1059,8 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { 
		ipareg_construct_endp_init_nat_n, ipareg_parse_dummy,

		0x0000080C, 0x70},

	[IPA_HW_v3_0][IPA_ENDP_INIT_CTRL_n] = {

		ipareg_construct_endp_init_ctrl_n, ipareg_parse_dummy,

		ipareg_construct_endp_init_ctrl_n,

		ipareg_parse_endp_init_ctrl_n,

		0x00000800, 0x70},

	[IPA_HW_v3_0][IPA_ENDP_INIT_HOL_BLOCK_EN_n] = {

		ipareg_construct_endp_init_hol_block_en_n,