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Commit ac35d82c authored by Xiaogang Cui's avatar Xiaogang Cui Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add DCC device on msmthorium 



Add node to add support for Data Capture and Compare (DCC)
device on msmthorium.

Change-Id: Ib0456c7b0ce5692e0183683ce3fd9e274a56cc9b
Signed-off-by: default avatarXiaogang Cui <xiaogang@codeaurora.org>
parent eae11620

arch/arm/boot/dts/qcom/msmthorium-coresight.dtsi

+39 −2
Original line number Diff line number Diff line
@@ -826,6 +826,43 @@ 
		clock-names = "core_clk", "core_a_clk";

	};



	tpda: tpda@6003000 {

		compatible = "qcom,coresight-tpda";

		reg = <0x6003000 0x1000>;

		reg-names = "tpda-base";



		coresight-id = <52>;

		coresight-name = "coresight-tpda";

		coresight-nr-inports = <2>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <6>;



		qcom,tpda-atid = <64>;

		qcom,cmb-elem-size = <0 32>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	tpdm_dcc: tpdm@6110000 {

		compatible = "qcom,coresight-tpdm";

		reg = <0x6110000 0x1000>;

		reg-names = "tpdm-base";



		coresight-id = <53>;

		coresight-name = "coresight-tpdm-dcc";

		coresight-nr-inports = <1>;

		coresight-outports = <0>;

		coresight-child-list = <&tpda>;

		coresight-child-ports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	hwevent: hwevent@6101000 {

		compatible = "qcom,coresight-hwevent";

		reg = <0x6101000 0x148>,
@@ -841,7 +878,7 @@ 
			    "mm-wrapper-mux", "mm-wrapper-lockaccess",

			    "usbbam-mux", "blsp-mux";



		coresight-id = <52>;

		coresight-id = <54>;

		coresight-name = "coresight-hwevent";

		coresight-nr-inports = <0>;
@@ -857,7 +894,7 @@ 
		      <0xa600c 0x4>;

		reg-names = "fuse-base", "nidnt-fuse-base", "qpdi-fuse-base";



		coresight-id = <53>;

		coresight-id = <55>;

		coresight-name = "coresight-fuse";

		coresight-nr-inports = <0>;

	};

arch/arm/boot/dts/qcom/msmthorium.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -320,6 +320,18 @@ 
		#clock-cells = <1>;

	};



	dcc: dcc@b3000 {

		compatible = "qcom,dcc";

		reg = <0xb3000 0x1000>,

		      <0xb4000 0x2000>;

		reg-names = "dcc-base", "dcc-ram-base";



		clocks = <&clock_gcc clk_gcc_dcc_clk>;

		clock-names = "dcc_clk";



		qcom,save-reg;

	};



	qcom,ipc-spinlock@1905000 {

		compatible = "qcom,ipc-spinlock-sfpb";

		reg = <0x1905000 0x8000>;