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Commit ac0a5042 authored by Mike Frysinger's avatar Mike Frysinger
Browse files

Blackfin: punt duplicate SPORT MMR defines 



The common bfin_sport.h header now has unified definitions of these, so
stop polluting the global namespace.

Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent d4348c67

arch/blackfin/include/asm/bfin_sport.h

+0 −6
Original line number Diff line number Diff line
@@ -115,12 +115,6 @@ struct sport_register { 


#endif



/* Workaround defBF*.h SPORT MMRs till they get cleansed */

#undef DTYPE_NORM

#undef SLEN

#undef SP_WOFF

#undef SP_WSIZE



/* SPORT_TCR1 Masks */

#define TSPEN		0x0001	/* TX enable */

#define ITCLK		0x0002	/* Internal TX Clock Select */

arch/blackfin/mach-bf518/include/mach/defBF51x_base.h

+0 −82
Original line number Diff line number Diff line
@@ -913,88 +913,6 @@ 
#define PH6		0x0040

#define PH7		0x0080





/* *******************  SERIAL PORT MASKS  **************************************/

/* SPORTx_TCR1 Masks															*/

#define TSPEN		0x0001		/* Transmit Enable								*/

#define ITCLK		0x0002		/* Internal Transmit Clock Select				*/

#define DTYPE_NORM	0x0004		/* Data Format Normal							*/

#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/

#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/

#define TLSBIT		0x0010		/* Transmit Bit Order							*/

#define ITFS		0x0200		/* Internal Transmit Frame Sync Select			*/

#define TFSR		0x0400		/* Transmit Frame Sync Required Select			*/

#define DITFS		0x0800		/* Data-Independent Transmit Frame Sync Select	*/

#define LTFS		0x1000		/* Low Transmit Frame Sync Select				*/

#define LATFS		0x2000		/* Late Transmit Frame Sync Select				*/

#define TCKFE		0x4000		/* Clock Falling Edge Select					*/



/* SPORTx_TCR2 Masks and Macro													*/

#define SLEN(x)		((x)&0x1F)	/* SPORT TX Word Length (2 - 31)				*/

#define TXSE		0x0100		/* TX Secondary Enable							*/

#define TSFSE		0x0200		/* Transmit Stereo Frame Sync Enable			*/

#define TRFST		0x0400		/* Left/Right Order (1 = Right Channel 1st)		*/



/* SPORTx_RCR1 Masks															*/

#define RSPEN		0x0001		/* Receive Enable 								*/

#define IRCLK		0x0002		/* Internal Receive Clock Select 				*/

#define DTYPE_NORM	0x0004		/* Data Format Normal							*/

#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/

#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/

#define RLSBIT		0x0010		/* Receive Bit Order							*/

#define IRFS		0x0200		/* Internal Receive Frame Sync Select 			*/

#define RFSR		0x0400		/* Receive Frame Sync Required Select 			*/

#define LRFS		0x1000		/* Low Receive Frame Sync Select 				*/

#define LARFS		0x2000		/* Late Receive Frame Sync Select 				*/

#define RCKFE		0x4000		/* Clock Falling Edge Select 					*/



/* SPORTx_RCR2 Masks															*/

#define SLEN(x)		((x)&0x1F)	/* SPORT RX Word Length (2 - 31)				*/

#define RXSE		0x0100		/* RX Secondary Enable							*/

#define RSFSE		0x0200		/* RX Stereo Frame Sync Enable					*/

#define RRFST		0x0400		/* Right-First Data Order 						*/



/* SPORTx_STAT Masks															*/

#define RXNE		0x0001		/* Receive FIFO Not Empty Status				*/

#define RUVF		0x0002		/* Sticky Receive Underflow Status				*/

#define ROVF		0x0004		/* Sticky Receive Overflow Status				*/

#define TXF			0x0008		/* Transmit FIFO Full Status					*/

#define TUVF		0x0010		/* Sticky Transmit Underflow Status				*/

#define TOVF		0x0020		/* Sticky Transmit Overflow Status				*/

#define TXHRE		0x0040		/* Transmit Hold Register Empty					*/



/* SPORTx_MCMC1 Macros															*/

#define SP_WOFF(x)	((x) & 0x3FF) 	/* Multichannel Window Offset Field			*/



/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits						*/

#define SP_WSIZE(x)	(((((x)>>0x3)-1)&0xF) << 0xC)	/* Multichannel Window Size = (x/8)-1	*/



/* SPORTx_MCMC2 Masks															*/

#define REC_BYPASS	0x0000		/* Bypass Mode (No Clock Recovery)				*/

#define REC_2FROM4	0x0002		/* Recover 2 MHz Clock from 4 MHz Clock			*/

#define REC_8FROM16	0x0003		/* Recover 8 MHz Clock from 16 MHz Clock		*/

#define MCDTXPE		0x0004 		/* Multichannel DMA Transmit Packing			*/

#define MCDRXPE		0x0008 		/* Multichannel DMA Receive Packing				*/

#define MCMEN		0x0010 		/* Multichannel Frame Mode Enable				*/

#define FSDR		0x0080 		/* Multichannel Frame Sync to Data Relationship	*/

#define MFD_0		0x0000		/* Multichannel Frame Delay = 0					*/

#define MFD_1		0x1000		/* Multichannel Frame Delay = 1					*/

#define MFD_2		0x2000		/* Multichannel Frame Delay = 2					*/

#define MFD_3		0x3000		/* Multichannel Frame Delay = 3					*/

#define MFD_4		0x4000		/* Multichannel Frame Delay = 4					*/

#define MFD_5		0x5000		/* Multichannel Frame Delay = 5					*/

#define MFD_6		0x6000		/* Multichannel Frame Delay = 6					*/

#define MFD_7		0x7000		/* Multichannel Frame Delay = 7					*/

#define MFD_8		0x8000		/* Multichannel Frame Delay = 8					*/

#define MFD_9		0x9000		/* Multichannel Frame Delay = 9					*/

#define MFD_10		0xA000		/* Multichannel Frame Delay = 10				*/

#define MFD_11		0xB000		/* Multichannel Frame Delay = 11				*/

#define MFD_12		0xC000		/* Multichannel Frame Delay = 12				*/

#define MFD_13		0xD000		/* Multichannel Frame Delay = 13				*/

#define MFD_14		0xE000		/* Multichannel Frame Delay = 14				*/

#define MFD_15		0xF000		/* Multichannel Frame Delay = 15				*/





/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/

/* EBIU_AMGCTL Masks																	*/

#define AMCKEN			0x0001		/* Enable CLKOUT									*/

arch/blackfin/mach-bf527/include/mach/defBF52x_base.h

+0 −82
Original line number Diff line number Diff line
@@ -922,88 +922,6 @@ 
#define PH14	0x4000

#define PH15	0x8000





/* *******************  SERIAL PORT MASKS  **************************************/

/* SPORTx_TCR1 Masks															*/

#define TSPEN		0x0001		/* Transmit Enable								*/

#define ITCLK		0x0002		/* Internal Transmit Clock Select				*/

#define DTYPE_NORM	0x0004		/* Data Format Normal							*/

#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/

#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/

#define TLSBIT		0x0010		/* Transmit Bit Order							*/

#define ITFS		0x0200		/* Internal Transmit Frame Sync Select			*/

#define TFSR		0x0400		/* Transmit Frame Sync Required Select			*/

#define DITFS		0x0800		/* Data-Independent Transmit Frame Sync Select	*/

#define LTFS		0x1000		/* Low Transmit Frame Sync Select				*/

#define LATFS		0x2000		/* Late Transmit Frame Sync Select				*/

#define TCKFE		0x4000		/* Clock Falling Edge Select					*/



/* SPORTx_TCR2 Masks and Macro													*/

#define SLEN(x)		((x)&0x1F)	/* SPORT TX Word Length (2 - 31)				*/

#define TXSE		0x0100		/* TX Secondary Enable							*/

#define TSFSE		0x0200		/* Transmit Stereo Frame Sync Enable			*/

#define TRFST		0x0400		/* Left/Right Order (1 = Right Channel 1st)		*/



/* SPORTx_RCR1 Masks															*/

#define RSPEN		0x0001		/* Receive Enable 								*/

#define IRCLK		0x0002		/* Internal Receive Clock Select 				*/

#define DTYPE_NORM	0x0004		/* Data Format Normal							*/

#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/

#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/

#define RLSBIT		0x0010		/* Receive Bit Order							*/

#define IRFS		0x0200		/* Internal Receive Frame Sync Select 			*/

#define RFSR		0x0400		/* Receive Frame Sync Required Select 			*/

#define LRFS		0x1000		/* Low Receive Frame Sync Select 				*/

#define LARFS		0x2000		/* Late Receive Frame Sync Select 				*/

#define RCKFE		0x4000		/* Clock Falling Edge Select 					*/



/* SPORTx_RCR2 Masks															*/

#define SLEN(x)		((x)&0x1F)	/* SPORT RX Word Length (2 - 31)				*/

#define RXSE		0x0100		/* RX Secondary Enable							*/

#define RSFSE		0x0200		/* RX Stereo Frame Sync Enable					*/

#define RRFST		0x0400		/* Right-First Data Order 						*/



/* SPORTx_STAT Masks															*/

#define RXNE		0x0001		/* Receive FIFO Not Empty Status				*/

#define RUVF		0x0002		/* Sticky Receive Underflow Status				*/

#define ROVF		0x0004		/* Sticky Receive Overflow Status				*/

#define TXF			0x0008		/* Transmit FIFO Full Status					*/

#define TUVF		0x0010		/* Sticky Transmit Underflow Status				*/

#define TOVF		0x0020		/* Sticky Transmit Overflow Status				*/

#define TXHRE		0x0040		/* Transmit Hold Register Empty					*/



/* SPORTx_MCMC1 Macros															*/

#define SP_WOFF(x)	((x) & 0x3FF) 	/* Multichannel Window Offset Field			*/



/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits						*/

#define SP_WSIZE(x)	(((((x)>>0x3)-1)&0xF) << 0xC)	/* Multichannel Window Size = (x/8)-1	*/



/* SPORTx_MCMC2 Masks															*/

#define REC_BYPASS	0x0000		/* Bypass Mode (No Clock Recovery)				*/

#define REC_2FROM4	0x0002		/* Recover 2 MHz Clock from 4 MHz Clock			*/

#define REC_8FROM16	0x0003		/* Recover 8 MHz Clock from 16 MHz Clock		*/

#define MCDTXPE		0x0004 		/* Multichannel DMA Transmit Packing			*/

#define MCDRXPE		0x0008 		/* Multichannel DMA Receive Packing				*/

#define MCMEN		0x0010 		/* Multichannel Frame Mode Enable				*/

#define FSDR		0x0080 		/* Multichannel Frame Sync to Data Relationship	*/

#define MFD_0		0x0000		/* Multichannel Frame Delay = 0					*/

#define MFD_1		0x1000		/* Multichannel Frame Delay = 1					*/

#define MFD_2		0x2000		/* Multichannel Frame Delay = 2					*/

#define MFD_3		0x3000		/* Multichannel Frame Delay = 3					*/

#define MFD_4		0x4000		/* Multichannel Frame Delay = 4					*/

#define MFD_5		0x5000		/* Multichannel Frame Delay = 5					*/

#define MFD_6		0x6000		/* Multichannel Frame Delay = 6					*/

#define MFD_7		0x7000		/* Multichannel Frame Delay = 7					*/

#define MFD_8		0x8000		/* Multichannel Frame Delay = 8					*/

#define MFD_9		0x9000		/* Multichannel Frame Delay = 9					*/

#define MFD_10		0xA000		/* Multichannel Frame Delay = 10				*/

#define MFD_11		0xB000		/* Multichannel Frame Delay = 11				*/

#define MFD_12		0xC000		/* Multichannel Frame Delay = 12				*/

#define MFD_13		0xD000		/* Multichannel Frame Delay = 13				*/

#define MFD_14		0xE000		/* Multichannel Frame Delay = 14				*/

#define MFD_15		0xF000		/* Multichannel Frame Delay = 15				*/





/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/

/* EBIU_AMGCTL Masks																	*/

#define AMCKEN			0x0001		/* Enable CLKOUT									*/

arch/blackfin/mach-bf533/include/mach/defBF532.h

+0 −92
Original line number Diff line number Diff line
@@ -509,98 +509,6 @@ 
#define IREN_P	0x01

#define UCEN_P	0x00



/* **********  SERIAL PORT MASKS  ********************** */



/* SPORTx_TCR1 Masks */

#define TSPEN    0x0001		/* TX enable  */

#define ITCLK    0x0002		/* Internal TX Clock Select  */

#define TDTYPE   0x000C		/* TX Data Formatting Select */

#define DTYPE_NORM	0x0000		/* Data Format Normal							*/

#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/

#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/

#define TLSBIT   0x0010		/* TX Bit Order */

#define ITFS     0x0200		/* Internal TX Frame Sync Select  */

#define TFSR     0x0400		/* TX Frame Sync Required Select  */

#define DITFS    0x0800		/* Data Independent TX Frame Sync Select  */

#define LTFS     0x1000		/* Low TX Frame Sync Select  */

#define LATFS    0x2000		/* Late TX Frame Sync Select  */

#define TCKFE    0x4000		/* TX Clock Falling Edge Select  */



/* SPORTx_TCR2 Masks */

#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \

    defined(__ADSPBF533__)

# define SLEN	    0x001F	/*TX Word Length  */

#else

# define SLEN(x)		((x)&0x1F)	/* SPORT TX Word Length (2 - 31)				*/

#endif

#define TXSE        0x0100	/*TX Secondary Enable */

#define TSFSE       0x0200	/*TX Stereo Frame Sync Enable */

#define TRFST       0x0400	/*TX Right-First Data Order  */



/* SPORTx_RCR1 Masks */

#define RSPEN    0x0001		/* RX enable  */

#define IRCLK    0x0002		/* Internal RX Clock Select  */

#define RDTYPE   0x000C		/* RX Data Formatting Select */

#define DTYPE_NORM	0x0000		/* no companding							*/

#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/

#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/

#define RLSBIT   0x0010		/* RX Bit Order */

#define IRFS     0x0200		/* Internal RX Frame Sync Select  */

#define RFSR     0x0400		/* RX Frame Sync Required Select  */

#define LRFS     0x1000		/* Low RX Frame Sync Select  */

#define LARFS    0x2000		/* Late RX Frame Sync Select  */

#define RCKFE    0x4000		/* RX Clock Falling Edge Select  */



/* SPORTx_RCR2 Masks */

/* SLEN defined above */

#define RXSE        0x0100	/*RX Secondary Enable */

#define RSFSE       0x0200	/*RX Stereo Frame Sync Enable */

#define RRFST       0x0400	/*Right-First Data Order  */



/*SPORTx_STAT Masks */

#define RXNE		0x0001	/*RX FIFO Not Empty Status */

#define RUVF	    	0x0002	/*RX Underflow Status */

#define ROVF		0x0004	/*RX Overflow Status */

#define TXF		0x0008	/*TX FIFO Full Status */

#define TUVF         	0x0010	/*TX Underflow Status */

#define TOVF         	0x0020	/*TX Overflow Status */

#define TXHRE        	0x0040	/*TX Hold Register Empty */



/*SPORTx_MCMC1 Masks */

#define SP_WSIZE		0x0000F000	/*Multichannel Window Size Field */

#define SP_WOFF		0x000003FF	/*Multichannel Window Offset Field */

/* SPORTx_MCMC1 Macros															*/

#define SET_SP_WOFF(x)	((x) & 0x3FF) 	/* Multichannel Window Offset Field			*/

/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits						*/

#define SET_SP_WSIZE(x)	(((((x)>>0x3)-1)&0xF) << 0xC)	/* Multichannel Window Size = (x/8)-1	*/



/*SPORTx_MCMC2 Masks */

#define MCCRM		0x00000003 	/*Multichannel Clock Recovery Mode */

#define REC_BYPASS	0x0000		/* Bypass Mode (No Clock Recovery)				*/

#define REC_2FROM4	0x0002		/* Recover 2 MHz Clock from 4 MHz Clock			*/

#define REC_8FROM16	0x0003		/* Recover 8 MHz Clock from 16 MHz Clock		*/

#define MCDTXPE		0x00000004 	/*Multichannel DMA Transmit Packing */

#define MCDRXPE		0x00000008 	/*Multichannel DMA Receive Packing */

#define MCMEN		0x00000010 	/*Multichannel Frame Mode Enable */

#define FSDR		0x00000080 	/*Multichannel Frame Sync to Data Relationship */

#define MFD		0x0000F000 	/*Multichannel Frame Delay    */

#define MFD_0		0x0000		/* Multichannel Frame Delay = 0					*/

#define MFD_1		0x1000		/* Multichannel Frame Delay = 1					*/

#define MFD_2		0x2000		/* Multichannel Frame Delay = 2					*/

#define MFD_3		0x3000		/* Multichannel Frame Delay = 3					*/

#define MFD_4		0x4000		/* Multichannel Frame Delay = 4					*/

#define MFD_5		0x5000		/* Multichannel Frame Delay = 5					*/

#define MFD_6		0x6000		/* Multichannel Frame Delay = 6					*/

#define MFD_7		0x7000		/* Multichannel Frame Delay = 7					*/

#define MFD_8		0x8000		/* Multichannel Frame Delay = 8					*/

#define MFD_9		0x9000		/* Multichannel Frame Delay = 9					*/

#define MFD_10		0xA000		/* Multichannel Frame Delay = 10				*/

#define MFD_11		0xB000		/* Multichannel Frame Delay = 11				*/

#define MFD_12		0xC000		/* Multichannel Frame Delay = 12				*/

#define MFD_13		0xD000		/* Multichannel Frame Delay = 13				*/

#define MFD_14		0xE000		/* Multichannel Frame Delay = 14				*/

#define MFD_15		0xF000		/* Multichannel Frame Delay = 15				*/



/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */



/*  PPI_CONTROL Masks         */

arch/blackfin/mach-bf537/include/mach/defBF534.h

+0 −80
Original line number Diff line number Diff line
@@ -1241,86 +1241,6 @@ 
#define PH14	0x4000

#define PH15	0x8000



/* *******************  SERIAL PORT MASKS  **************************************/

/* SPORTx_TCR1 Masks															*/

#define TSPEN		0x0001	/* Transmit Enable                                                              */

#define ITCLK		0x0002	/* Internal Transmit Clock Select                               */

#define DTYPE_NORM	0x0004	/* Data Format Normal                                                   */

#define DTYPE_ULAW	0x0008	/* Compand Using u-Law                                                  */

#define DTYPE_ALAW	0x000C	/* Compand Using A-Law                                                  */

#define TLSBIT		0x0010	/* Transmit Bit Order                                                   */

#define ITFS		0x0200	/* Internal Transmit Frame Sync Select                  */

#define TFSR		0x0400	/* Transmit Frame Sync Required Select                  */

#define DITFS		0x0800	/* Data-Independent Transmit Frame Sync Select  */

#define LTFS		0x1000	/* Low Transmit Frame Sync Select                               */

#define LATFS		0x2000	/* Late Transmit Frame Sync Select                              */

#define TCKFE		0x4000	/* Clock Falling Edge Select                                    */



/* SPORTx_TCR2 Masks and Macro													*/

#define SLEN(x)		((x)&0x1F)	/* SPORT TX Word Length (2 - 31)                                */

#define TXSE		0x0100	/* TX Secondary Enable                                                  */

#define TSFSE		0x0200	/* Transmit Stereo Frame Sync Enable                    */

#define TRFST		0x0400	/* Left/Right Order (1 = Right Channel 1st)             */



/* SPORTx_RCR1 Masks															*/

#define RSPEN		0x0001	/* Receive Enable                                                               */

#define IRCLK		0x0002	/* Internal Receive Clock Select                                */

#define DTYPE_NORM	0x0004	/* Data Format Normal                                                   */

#define DTYPE_ULAW	0x0008	/* Compand Using u-Law                                                  */

#define DTYPE_ALAW	0x000C	/* Compand Using A-Law                                                  */

#define RLSBIT		0x0010	/* Receive Bit Order                                                    */

#define IRFS		0x0200	/* Internal Receive Frame Sync Select                   */

#define RFSR		0x0400	/* Receive Frame Sync Required Select                   */

#define LRFS		0x1000	/* Low Receive Frame Sync Select                                */

#define LARFS		0x2000	/* Late Receive Frame Sync Select                               */

#define RCKFE		0x4000	/* Clock Falling Edge Select                                    */



/* SPORTx_RCR2 Masks															*/

#define SLEN(x)		((x)&0x1F)	/* SPORT RX Word Length (2 - 31)                                */

#define RXSE		0x0100	/* RX Secondary Enable                                                  */

#define RSFSE		0x0200	/* RX Stereo Frame Sync Enable                                  */

#define RRFST		0x0400	/* Right-First Data Order                                               */



/* SPORTx_STAT Masks															*/

#define RXNE		0x0001	/* Receive FIFO Not Empty Status                                */

#define RUVF		0x0002	/* Sticky Receive Underflow Status                              */

#define ROVF		0x0004	/* Sticky Receive Overflow Status                               */

#define TXF			0x0008	/* Transmit FIFO Full Status                                    */

#define TUVF		0x0010	/* Sticky Transmit Underflow Status                             */

#define TOVF		0x0020	/* Sticky Transmit Overflow Status                              */

#define TXHRE		0x0040	/* Transmit Hold Register Empty                                 */



/* SPORTx_MCMC1 Macros															*/

#define SP_WOFF(x)		((x) & 0x3FF)	/* Multichannel Window Offset Field                     */



/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits						*/

#define SP_WSIZE(x)	(((((x)>>0x3)-1)&0xF) << 0xC)	/* Multichannel Window Size = (x/8)-1   */



/* SPORTx_MCMC2 Masks															*/

#define REC_BYPASS	0x0000	/* Bypass Mode (No Clock Recovery)                              */

#define REC_2FROM4	0x0002	/* Recover 2 MHz Clock from 4 MHz Clock                 */

#define REC_8FROM16	0x0003	/* Recover 8 MHz Clock from 16 MHz Clock                */

#define MCDTXPE		0x0004	/* Multichannel DMA Transmit Packing                    */

#define MCDRXPE		0x0008	/* Multichannel DMA Receive Packing                             */

#define MCMEN		0x0010	/* Multichannel Frame Mode Enable                               */

#define FSDR		0x0080	/* Multichannel Frame Sync to Data Relationship */

#define MFD_0		0x0000	/* Multichannel Frame Delay = 0                                 */

#define MFD_1		0x1000	/* Multichannel Frame Delay = 1                                 */

#define MFD_2		0x2000	/* Multichannel Frame Delay = 2                                 */

#define MFD_3		0x3000	/* Multichannel Frame Delay = 3                                 */

#define MFD_4		0x4000	/* Multichannel Frame Delay = 4                                 */

#define MFD_5		0x5000	/* Multichannel Frame Delay = 5                                 */

#define MFD_6		0x6000	/* Multichannel Frame Delay = 6                                 */

#define MFD_7		0x7000	/* Multichannel Frame Delay = 7                                 */

#define MFD_8		0x8000	/* Multichannel Frame Delay = 8                                 */

#define MFD_9		0x9000	/* Multichannel Frame Delay = 9                                 */

#define MFD_10		0xA000	/* Multichannel Frame Delay = 10                                */

#define MFD_11		0xB000	/* Multichannel Frame Delay = 11                                */

#define MFD_12		0xC000	/* Multichannel Frame Delay = 12                                */

#define MFD_13		0xD000	/* Multichannel Frame Delay = 13                                */

#define MFD_14		0xE000	/* Multichannel Frame Delay = 14                                */

#define MFD_15		0xF000	/* Multichannel Frame Delay = 15                                */



/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/

/* EBIU_AMGCTL Masks																	*/

#define AMCKEN			0x0001	/* Enable CLKOUT                                                                        */