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Commit ab9c975d authored by Alok Chauhan's avatar Alok Chauhan
Browse files

ARM: dts: msm: Update the bus driver enum variables 



Update the bus driver enum variables to accommodate
missing changes.

Change-Id: Ic163d8f574ad11ba234936a30db43a904dbcc2d8
Signed-off-by: default avatarAlok Chauhan <alokc@codeaurora.org>
parent 8e6fdb81

include/dt-bindings/msm/msm-bus-ids.h

+394 −363
Original line number Diff line number Diff line
@@ -63,6 +63,7 @@ 
#define	MSM_BUS_MASTER_JPEG_DEC 27

#define	MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28

#define	MSM_BUS_MASTER_VFE 29

#define	MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE

#define	MSM_BUS_MASTER_VPE 30

#define	MSM_BUS_MASTER_JPEG_ENC 31

#define	MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32
@@ -142,7 +143,9 @@ 
#define	MSM_BUS_MASTER_CPP 106

#define	MSM_BUS_MASTER_AUDIO 107

#define	MSM_BUS_MASTER_PCIE_2 108

#define	MSM_BUS_MASTER_LAST 114

#define	MSM_BUS_MASTER_VFE1 109

#define MSM_BUS_MASTER_XM_USB_HS1 110

#define	MSM_BUS_MASTER_LAST 111



#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB

#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB
@@ -213,8 +216,9 @@ 
#define	MSM_BUS_A1NOC_SNOC_MAS 10063

#define	MSM_BUS_A2NOC_SNOC_MAS 10064

#define	MSM_BUS_A2NOC_SNOC_SLV 10065

#define	MSM_BUS_A0NOC_QDSS_INT 10066

#define	MSM_BUS_INT_LAST 10067

#define	MSM_BUS_SNOC_INT_2 10066

#define	MSM_BUS_A0NOC_QDSS_INT	10067

#define	MSM_BUS_INT_LAST 10068



#define	MSM_BUS_INT_TEST_ID	20000

#define	MSM_BUS_INT_TEST_LAST	20050
@@ -449,6 +453,7 @@ 
#define	ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO

#define	ICBID_MASTER_VIDEO_P1 10

#define	ICBID_MASTER_VFE 11

#define	ICBID_MASTER_VFE0 ICBID_MASTER_VFE

#define	ICBID_MASTER_CNOC_ONOC_CFG 12

#define	ICBID_MASTER_JPEG_OCMEM 13

#define	ICBID_MASTER_MDP_OCMEM 14
@@ -459,6 +464,7 @@ 
#define	ICBID_MASTER_QDSS_BAM 19

#define	ICBID_MASTER_SNOC_CFG 20

#define	ICBID_MASTER_BIMC_SNOC 21

#define	ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC

#define	ICBID_MASTER_CNOC_SNOC 22

#define	ICBID_MASTER_CRYPTO 23

#define	ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO
@@ -552,29 +558,42 @@ 
#define	ICBID_MASTER_BIMC_INT_1 105

#define	ICBID_MASTER_CAMERA 106

#define	ICBID_MASTER_RICA 107

#define ICBID_MASTER_PCNOC_S_5 129

#define ICBID_MASTER_PCNOC_INT_2 124

#define ICBID_MASTER_PCNOC_INT_3 125

#define ICBID_MASTER_PCNOC_INT_4 126

#define ICBID_MASTER_PCNOC_INT_5 127

#define ICBID_MASTER_PCNOC_INT_6 128

#define ICBID_MASTER_PCIE_2 119

#define ICBID_MASTER_MASTER_CNOC_A1NOC 116

#define	ICBID_MASTER_SNOC_BIMC_2 108

#define	ICBID_MASTER_BIMC_SNOC_1 109

#define	ICBID_MASTER_A0NOC_SNOC 110

#define	ICBID_MASTER_A1NOC_SNOC 111

#define	ICBID_MASTER_A2NOC_SNOC 112

#define	ICBID_MASTER_PIMEM 113

#define	ICBID_MASTER_SNOC_VMEM 114

#define	ICBID_MASTER_CPP 115

#define	ICBID_MASTER_CNOC_A1NOC 116

#define	ICBID_MASTER_PNOC_A1NOC 117

#define	ICBID_MASTER_HMSS 118

#define	ICBID_MASTER_PCIE_2 119

#define	ICBID_MASTER_ROTATOR 120

#define ICBID_MASTER_SNOC_VMEM 114

#define	ICBID_MASTER_VENUS_VMEM 121

#define ICBID_MASTER_HMSS 118

#define ICBID_MASTER_BIMC_SNOC_1 109

#define ICBID_MASTER_CNOC_A1NOC 116

#define ICBID_MASTER_CPP 115

#define	ICBID_MASTER_DCC 122

#define	ICBID_MASTER_MCDMA 123

#define	ICBID_MASTER_PCNOC_INT_2 124

#define	ICBID_MASTER_PCNOC_INT_3 125

#define	ICBID_MASTER_PCNOC_INT_4 126

#define	ICBID_MASTER_PCNOC_INT_5 127

#define	ICBID_MASTER_PCNOC_INT_6 128

#define	ICBID_MASTER_PCNOC_S_5 129

#define	ICBID_MASTER_SENSORS_AHB 130

#define	ICBID_MASTER_SENSORS_PROC 131

#define	ICBID_MASTER_QSPI 132

#define	ICBID_MASTER_VFE1 133

#define	ICBID_MASTER_SNOC_INT_2 134

#define	ICBID_MASTER_SMMNOC_BIMC 135

#define	ICBID_MASTER_CRVIRT_A1NOC 136

#define	ICBID_MASTER_XM_USB_HS1 137

#define	ICBID_MASTER_XI_USB_HS1 138



#define	ICBID_SLAVE_EBI1 0

#define	ICBID_SLAVE_APPSS_L2 1

#define	ICBID_SLAVE_BIMC_SNOC 2

#define	ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC

#define	ICBID_SLAVE_CAMERA_CFG 3

#define	ICBID_SLAVE_DISPLAY_CFG 4

#define	ICBID_SLAVE_OCMEM_CFG 5
@@ -719,27 +738,16 @@ 
#define	ICBID_SLAVE_BIMC_INT_0 134

#define	ICBID_SLAVE_BIMC_INT_1 135

#define	ICBID_SLAVE_RICA_CFG 136

#define ICBID_SLAVE_PCNOC_S_5 189

#define ICBID_SLAVE_PCNOC_S_7 124

#define ICBID_SLAVE_PCNOC_INT_2 184

#define ICBID_SLAVE_PCNOC_INT_3 185

#define ICBID_SLAVE_PCNOC_INT_4 186

#define ICBID_SLAVE_PCNOC_INT_5 187

#define ICBID_SLAVE_PCNOC_INT_6 188

#define ICBID_SLAVE_USB3_PHY_CFG 182

#define ICBID_SLAVE_IPA_CFG 183

#define	ICBID_SLAVE_SNOC_BIMC_2 137

#define	ICBID_SLAVE_BIMC_SNOC_1 138

#define	ICBID_SLAVE_PNOC_A1NOC 139

#define	ICBID_SLAVE_SNOC_VMEM 140

#define	ICBID_SLAVE_A0NOC_SNOC 141

#define	ICBID_SLAVE_A1NOC_SNOC 142

#define	ICBID_SLAVE_A2NOC_SNOC 143

#define ICBID_SLAVE_BIMC_SNOC_1 138

#define ICBID_SLAVE_PIMEM 167

#define ICBID_SLAVE_PIMEM_CFG 168

#define ICBID_SLAVE_DCC_CFG 155

#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168

#define	ICBID_SLAVE_A0NOC_CFG 144

#define ICBID_SLAVE_PCIE_2_CFG 165

#define ICBID_SLAVE_PCIE20_AHB2PHY 163

#define ICBID_SLAVE_PCIE_2 164

#define	ICBID_SLAVE_A0NOC_MPU_CFG 145

#define	ICBID_SLAVE_A0NOC_SMMU_CFG 146

#define	ICBID_SLAVE_A1NOC_CFG 147

#define	ICBID_SLAVE_A1NOC_MPU_CFG 148

#define	ICBID_SLAVE_A1NOC_SMMU_CFG 149
@@ -747,28 +755,51 @@ 
#define	ICBID_SLAVE_A2NOC_MPU_CFG 151

#define	ICBID_SLAVE_A2NOC_SMMU_CFG 152

#define	ICBID_SLAVE_AHB2PHY 153

#define ICBID_SLAVE_HMSS_L3 161

#define ICBID_SLAVE_LPASS_SMMU_CFG 161

#define ICBID_SLAVE_MMAGIC_CFG 162

#define ICBID_SLAVE_SSC_CFG 177

#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178

#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156

#define	ICBID_SLAVE_CAMERA_THROTTLE_CFG 154

#define	ICBID_SLAVE_DCC_CFG 155

#define	ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156

#define	ICBID_SLAVE_DSA_CFG 157

#define	ICBID_SLAVE_DSA_MPU_CFG 158

#define	ICBID_SLAVE_SSC_MPU_CFG 159

#define	ICBID_SLAVE_HMSS_L3 160

#define	ICBID_SLAVE_LPASS_SMMU_CFG 161

#define	ICBID_SLAVE_MMAGIC_CFG 162

#define	ICBID_SLAVE_PCIE20_AHB2PHY 163

#define	ICBID_SLAVE_PCIE_2 164

#define	ICBID_SLAVE_PCIE_2_CFG 165

#define	ICBID_SLAVE_PIMEM 166

#define	ICBID_SLAVE_PIMEM_CFG 167

#define	ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168

#define	ICBID_SLAVE_RBCPR_CX 169

#define	ICBID_SLAVE_RBCPR_MX 170

#define	ICBID_SLAVE_SMMU_CPP_CFG 171

#define	ICBID_SLAVE_SMMU_JPEG_CFG 172

#define	ICBID_SLAVE_SMMU_MDP_CFG 173

#define	ICBID_SLAVE_SMMU_ROTATOR_CFG 174

#define	ICBID_SLAVE_SMMU_VENUS_CFG 175

#define	ICBID_SLAVE_SMMU_VFE_CFG 176

#define ICBID_SLAVE_A0NOC_MPU_CFG 145

#define ICBID_SLAVE_A0NOC_SMMU_CFG 146

#define ICBID_SLAVE_VMEM_CFG 180

#define	ICBID_SLAVE_SSC_CFG 177

#define	ICBID_SLAVE_VENUS_THROTTLE_CFG 178

#define	ICBID_SLAVE_VMEM 179

#define ICBID_SLAVE_PNOC_A1NOC 139

#define ICBID_SLAVE_SNOC_VMEM 140

#define ICBID_SLAVE_RBCPR_MX 170

#define ICBID_SLAVE_RBCPR_CX 169

#define	ICBID_SLAVE_VMEM_CFG 180

#define	ICBID_SLAVE_QDSS_MPU_CFG 181

#define	ICBID_SLAVE_USB3_PHY_CFG 182

#define	ICBID_SLAVE_IPA_CFG 183

#define	ICBID_SLAVE_PCNOC_INT_2 184

#define	ICBID_SLAVE_PCNOC_INT_3 185

#define	ICBID_SLAVE_PCNOC_INT_4 186

#define	ICBID_SLAVE_PCNOC_INT_5 187

#define	ICBID_SLAVE_PCNOC_INT_6 188

#define	ICBID_SLAVE_PCNOC_S_5 189

#define	ICBID_SLAVE_QSPI 190

#define	ICBID_SLAVE_A1NOC_MS_MPU_CFG 191

#define	ICBID_SLAVE_A2NOC_MS_MPU_CFG 192

#define	ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193

#define	ICBID_SLAVE_MSS_MPU_CFG 194

#define	ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195

#define	ICBID_SLAVE_SKL 196

#define	ICBID_SLAVE_SNOC_INT_2 197

#define	ICBID_SLAVE_SMMNOC_BIMC 198

#define	ICBID_SLAVE_CRVIRT_A1NOC 199



#endif