Commit ab53c267 authored May 23, 2014 by Ville Syrjälä Committed by Daniel Vetter Jun 11, 2014

drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV



CHV uses the gen8 shadow register mechanism so we shouldn't be
checking the GT FIFO status.

This effectively removes the posting read, so add an explicit
posting read using FORCEWAKE_ACK_VLV (which is what use in
vlv_forcewake_reset()).

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent 3f4e3495

drivers/gpu/drm/i915/intel_uncore.c

+4 −3

Original line number	Diff line number	Diff line
		@@ -250,9 +250,10 @@ static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
		__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
		_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));

		/* The below doubles as a POSTING_READ */
		/* something from same cacheline, but !FORCEWAKE_VLV */
		__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
		if (!IS_CHERRYVIEW(dev_priv->dev))
		gen6_gt_check_fifodbg(dev_priv);

		}

		static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)