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Commit aaed44e1 authored by Mark Brown's avatar Mark Brown Committed by Kukjin Kim
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ARM: S3C64XX: Correct reservation of GPIOs for CPU module on Cragganmore 



The gpio_base for the PMIC on the CPU module was being incorrectly set to
be the same as that for the CODEC causing the two GPIO drivers to collide.

Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 4ff13995

arch/arm/mach-s3c64xx/include/mach/crag6410.h

+2 −1
Original line number Diff line number Diff line
@@ -19,5 +19,6 @@ 
#define PCA935X_GPIO_BASE		GPIO_BOARD_START

#define CODEC_GPIO_BASE			(GPIO_BOARD_START + 8)

#define GLENFARCLAS_PMIC_GPIO_BASE	(GPIO_BOARD_START + 16)

#define BANFF_PMIC_GPIO_BASE		(GPIO_BOARD_START + 32)



#endif

arch/arm/mach-s3c64xx/mach-crag6410.c

+1 −1
Original line number Diff line number Diff line
@@ -500,7 +500,7 @@ static struct wm831x_touch_pdata touch_pdata __initdata = { 
static struct wm831x_pdata crag_pmic_pdata __initdata = {

	.wm831x_num = 1,

	.irq_base = BANFF_PMIC_IRQ_BASE,

	.gpio_base = GPIO_BOARD_START + 8,

	.gpio_base = BANFF_PMIC_GPIO_BASE,



	.backup = &banff_backup_pdata,