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Commit aad3d14d authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Add DP training pattern 3 for CHV 



CHV supports DP training pattern 3. Add the required stuff.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a5043453

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -3489,6 +3489,8 @@ enum punit_power_well { 
#define   DP_LINK_TRAIN_OFF		(3 << 28)

#define   DP_LINK_TRAIN_MASK		(3 << 28)

#define   DP_LINK_TRAIN_SHIFT		28

#define   DP_LINK_TRAIN_PAT_3_CHV	(1 << 14)

#define   DP_LINK_TRAIN_MASK_CHV	((3 << 28)|(1<<14))



/* CPT Link training mode */

#define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)

drivers/gpu/drm/i915/intel_dp.c

+14 −4
Original line number Diff line number Diff line
@@ -2959,6 +2959,9 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, 
		}



	} else {

		if (IS_CHERRYVIEW(dev))

			*DP &= ~DP_LINK_TRAIN_MASK_CHV;

		else

			*DP &= ~DP_LINK_TRAIN_MASK;



		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
@@ -2972,8 +2975,12 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, 
			*DP |= DP_LINK_TRAIN_PAT_2;

			break;

		case DP_TRAINING_PATTERN_3:

			if (IS_CHERRYVIEW(dev)) {

				*DP |= DP_LINK_TRAIN_PAT_3_CHV;

			} else {

				DRM_ERROR("DP training pattern 3 not supported\n");

				*DP |= DP_LINK_TRAIN_PAT_2;

			}

			break;

		}

	}
@@ -3260,6 +3267,9 @@ intel_dp_link_down(struct intel_dp *intel_dp) 
		DP &= ~DP_LINK_TRAIN_MASK_CPT;

		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);

	} else {

		if (IS_CHERRYVIEW(dev))

			DP &= ~DP_LINK_TRAIN_MASK_CHV;

		else

			DP &= ~DP_LINK_TRAIN_MASK;

		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);

	}