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Commit aa71fa3c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge remote branch 'nouveau/for-airlied' into drm-next-stage 

* nouveau/for-airlied: (25 commits)
  drm/nouveau: use ALIGN instead of open coding it
  drm/nouveau: report unknown connector state if lid closed
  drm/nouveau: support version 0x20 displayport tables
  drm/nouveau: Fix noaccel/nofbaccel option descriptions.
  drm/nv50: Implement ctxprog/state generation.
  drm/nouveau: use dcb connector types throughout the driver
  drm/nv50: enable hpd on any connector we know the gpio line for
  drm/nouveau: use dcb connector table for creating drm connectors
  drm/nouveau: construct a connector table for cards that lack a real one
  drm/nouveau: check for known dcb connector types
  drm/nouveau: parse dcb gpio/connector tables after encoders
  drm/nouveau: reorganise bios header, add dcb connector type enums
  drm/nouveau: merge nvbios and nouveau_bios_info
  drm/nouveau: merge parsed_dcb and bios_parsed_dcb into dcb_table
  drm/nouveau: rename parsed_dcb_gpio to dcb_gpio_table
  drm/nouveau: allow retrieval of vbios image from debugfs
  drm/nouveau: fix missing spin_unlock in failure path
  drm/nouveau: fix i2ctable bounds checking
  drm/nouveau: fix nouveau_i2c_find bounds checking
  drm/nouveau: fix pramdac_table range checking
  ...

Conflicts:
	drivers/gpu/drm/nouveau/nouveau_gem.c
parents 79fa9eb7 3bfc7d22

drivers/gpu/drm/nouveau/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ 
             nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \

             nv04_graph.o nv10_graph.o nv20_graph.o \

             nv40_graph.o nv50_graph.o \

             nv40_grctx.o \

             nv40_grctx.o nv50_grctx.o \

             nv04_instmem.o nv50_instmem.o \

             nv50_crtc.o nv50_dac.o nv50_sor.o \

             nv50_cursor.o nv50_display.o nv50_fbcon.o \

drivers/gpu/drm/nouveau/nouveau_bios.c

+200 −139

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/nouveau/nouveau_bios.h

+66 −60
Original line number Diff line number Diff line
@@ -34,9 +34,67 @@ 


#define DCB_LOC_ON_CHIP 0



struct dcb_i2c_entry {

	uint8_t port_type;

	uint8_t read, write;

	struct nouveau_i2c_chan *chan;

};



enum dcb_gpio_tag {

	DCB_GPIO_TVDAC0 = 0xc,

	DCB_GPIO_TVDAC1 = 0x2d,

};



struct dcb_gpio_entry {

	enum dcb_gpio_tag tag;

	int line;

	bool invert;

};



struct dcb_gpio_table {

	int entries;

	struct dcb_gpio_entry entry[DCB_MAX_NUM_GPIO_ENTRIES];

};



enum dcb_connector_type {

	DCB_CONNECTOR_VGA = 0x00,

	DCB_CONNECTOR_TV_0 = 0x10,

	DCB_CONNECTOR_TV_1 = 0x11,

	DCB_CONNECTOR_TV_3 = 0x13,

	DCB_CONNECTOR_DVI_I = 0x30,

	DCB_CONNECTOR_DVI_D = 0x31,

	DCB_CONNECTOR_LVDS = 0x40,

	DCB_CONNECTOR_DP = 0x46,

	DCB_CONNECTOR_eDP = 0x47,

	DCB_CONNECTOR_HDMI_0 = 0x60,

	DCB_CONNECTOR_HDMI_1 = 0x61,

	DCB_CONNECTOR_NONE = 0xff

};



struct dcb_connector_table_entry {

	uint32_t entry;

	enum dcb_connector_type type;

	uint8_t index;

	uint8_t gpio_tag;

};



struct dcb_connector_table {

	int entries;

	struct dcb_connector_table_entry entry[DCB_MAX_NUM_CONNECTOR_ENTRIES];

};



enum dcb_type {

	OUTPUT_ANALOG = 0,

	OUTPUT_TV = 1,

	OUTPUT_TMDS = 2,

	OUTPUT_LVDS = 3,

	OUTPUT_DP = 6,

	OUTPUT_ANY = -1

};



struct dcb_entry {

	int index;	/* may not be raw dcb index if merging has happened */

	uint8_t type;

	enum dcb_type type;

	uint8_t i2c_index;

	uint8_t heads;

	uint8_t connector;
@@ -71,69 +129,22 @@ struct dcb_entry { 
	bool i2c_upper_default;

};



struct dcb_i2c_entry {

	uint8_t port_type;

	uint8_t read, write;

	struct nouveau_i2c_chan *chan;

};

struct dcb_table {

	uint8_t version;



struct parsed_dcb {

	int entries;

	struct dcb_entry entry[DCB_MAX_NUM_ENTRIES];

	struct dcb_i2c_entry i2c[DCB_MAX_NUM_I2C_ENTRIES];

};



enum dcb_gpio_tag {

	DCB_GPIO_TVDAC0 = 0xc,

	DCB_GPIO_TVDAC1 = 0x2d,

};



struct dcb_gpio_entry {

	enum dcb_gpio_tag tag;

	int line;

	bool invert;

};



struct parsed_dcb_gpio {

	int entries;

	struct dcb_gpio_entry entry[DCB_MAX_NUM_GPIO_ENTRIES];

};



struct dcb_connector_table_entry {

	uint32_t entry;

	uint8_t type;

	uint8_t index;

	uint8_t gpio_tag;

};



struct dcb_connector_table {

	int entries;

	struct dcb_connector_table_entry entry[DCB_MAX_NUM_CONNECTOR_ENTRIES];

};



struct bios_parsed_dcb {

	uint8_t version;



	struct parsed_dcb dcb;



	uint8_t *i2c_table;

	uint8_t i2c_default_indices;

	struct dcb_i2c_entry i2c[DCB_MAX_NUM_I2C_ENTRIES];



	uint16_t gpio_table_ptr;

	struct parsed_dcb_gpio gpio;

	struct dcb_gpio_table gpio;

	uint16_t connector_table_ptr;

	struct dcb_connector_table connector;

};



enum nouveau_encoder_type {

	OUTPUT_ANALOG = 0,

	OUTPUT_TV = 1,

	OUTPUT_TMDS = 2,

	OUTPUT_LVDS = 3,

	OUTPUT_DP = 6,

	OUTPUT_ANY = -1

};



enum nouveau_or {

	OUTPUT_A = (1 << 0),

	OUTPUT_B = (1 << 1),
@@ -190,8 +201,8 @@ struct pll_lims { 
	int refclk;

};



struct nouveau_bios_info {

	struct parsed_dcb *dcb;

struct nvbios {

	struct drm_device *dev;



	uint8_t chip_version;
@@ -199,11 +210,6 @@ struct nouveau_bios_info { 
	uint32_t tvdactestval;

	uint8_t digital_min_front_porch;

	bool fp_no_ddc;

};



struct nvbios {

	struct drm_device *dev;

	struct nouveau_bios_info pub;



	struct mutex lock;
@@ -234,7 +240,7 @@ struct nvbios { 
	uint16_t some_script_ptr; /* BIT I + 14 */

	uint16_t init96_tbl_ptr; /* BIT I + 16 */



	struct bios_parsed_dcb bdcb;

	struct dcb_table dcb;



	struct {

		int crtchead;

drivers/gpu/drm/nouveau/nouveau_calc.c

+2 −2
Original line number Diff line number Diff line
@@ -274,7 +274,7 @@ getMNP_single(struct drm_device *dev, struct pll_lims *pll_lim, int clk, 
	 * returns calculated clock

	 */

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	int cv = dev_priv->vbios->chip_version;

	int cv = dev_priv->vbios.chip_version;

	int minvco = pll_lim->vco1.minfreq, maxvco = pll_lim->vco1.maxfreq;

	int minM = pll_lim->vco1.min_m, maxM = pll_lim->vco1.max_m;

	int minN = pll_lim->vco1.min_n, maxN = pll_lim->vco1.max_n;
@@ -373,7 +373,7 @@ getMNP_double(struct drm_device *dev, struct pll_lims *pll_lim, int clk, 
	 * returns calculated clock

	 */

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	int chip_version = dev_priv->vbios->chip_version;

	int chip_version = dev_priv->vbios.chip_version;

	int minvco1 = pll_lim->vco1.minfreq, maxvco1 = pll_lim->vco1.maxfreq;

	int minvco2 = pll_lim->vco2.minfreq, maxvco2 = pll_lim->vco2.maxfreq;

	int minU1 = pll_lim->vco1.min_inputfreq, minU2 = pll_lim->vco2.min_inputfreq;

drivers/gpu/drm/nouveau/nouveau_channel.c

+29 −10
Original line number Diff line number Diff line
@@ -35,22 +35,27 @@ nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan) 
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_bo *pb = chan->pushbuf_bo;

	struct nouveau_gpuobj *pushbuf = NULL;

	uint32_t start = pb->bo.mem.mm_node->start << PAGE_SHIFT;

	int ret;



	if (dev_priv->card_type >= NV_50) {

		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,

					     dev_priv->vm_end, NV_DMA_ACCESS_RO,

					     NV_DMA_TARGET_AGP, &pushbuf);

		chan->pushbuf_base = pb->bo.offset;

	} else

	if (pb->bo.mem.mem_type == TTM_PL_TT) {

		ret = nouveau_gpuobj_gart_dma_new(chan, 0,

						  dev_priv->gart_info.aper_size,

						  NV_DMA_ACCESS_RO, &pushbuf,

						  NULL);

		chan->pushbuf_base = start;

		chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT;

	} else

	if (dev_priv->card_type != NV_04) {

		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,

					     dev_priv->fb_available_size,

					     NV_DMA_ACCESS_RO,

					     NV_DMA_TARGET_VIDMEM, &pushbuf);

		chan->pushbuf_base = start;

		chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT;

	} else {

		/* NV04 cmdbuf hack, from original ddx.. not sure of it's

		 * exact reason for existing :)  PCI access to cmdbuf in
@@ -61,7 +66,7 @@ nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan) 
					     dev_priv->fb_available_size,

					     NV_DMA_ACCESS_RO,

					     NV_DMA_TARGET_PCI, &pushbuf);

		chan->pushbuf_base = start;

		chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT;

	}



	ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf, &chan->pushbuf);
@@ -275,9 +280,18 @@ nouveau_channel_free(struct nouveau_channel *chan) 
	 */

	nouveau_fence_fini(chan);



	/* Ensure the channel is no longer active on the GPU */

	/* This will prevent pfifo from switching channels. */

	pfifo->reassign(dev, false);



	/* We want to give pgraph a chance to idle and get rid of all potential

	 * errors. We need to do this before the lock, otherwise the irq handler

	 * is unable to process them.

	 */

	if (pgraph->channel(dev) == chan)

		nouveau_wait_for_idle(dev);



	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);



	pgraph->fifo_access(dev, false);

	if (pgraph->channel(dev) == chan)

		pgraph->unload_context(dev);
@@ -293,6 +307,8 @@ nouveau_channel_free(struct nouveau_channel *chan) 


	pfifo->reassign(dev, true);



	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);



	/* Release the channel's resources */

	nouveau_gpuobj_ref_del(dev, &chan->pushbuf);

	if (chan->pushbuf_bo) {
@@ -369,6 +385,14 @@ nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, 
		return ret;

	init->channel  = chan->id;



	if (chan->dma.ib_max)

		init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |

					NOUVEAU_GEM_DOMAIN_GART;

	else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)

		init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;

	else

		init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;



	init->subchan[0].handle = NvM2MF;

	if (dev_priv->card_type < NV_50)

		init->subchan[0].grclass = 0x0039;
@@ -408,7 +432,6 @@ nouveau_ioctl_fifo_free(struct drm_device *dev, void *data, 
 ***********************************/



struct drm_ioctl_desc nouveau_ioctls[] = {

	DRM_IOCTL_DEF(DRM_NOUVEAU_CARD_INIT, nouveau_ioctl_card_init, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),

	DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
@@ -418,13 +441,9 @@ struct drm_ioctl_desc nouveau_ioctls[] = { 
	DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF_CALL, nouveau_gem_ioctl_pushbuf_call, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PIN, nouveau_gem_ioctl_pin, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_UNPIN, nouveau_gem_ioctl_unpin, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF_CALL2, nouveau_gem_ioctl_pushbuf_call2, DRM_AUTH),

};



int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);