Merge "msm: mdss: Dither support in PingPong buffer" (a9ed8a62) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/video/msm/mdss/mdss_mdp_ctl.c

+11 −2

Original line number	Diff line number	Diff line
		@@ -3054,7 +3054,7 @@ int mdss_mdp_ctl_setup(struct mdss_mdp_ctl *ctl)
		{
		struct mdss_mdp_ctl *split_ctl;
		u32 width, height;
		int split_fb;
		int split_fb, rc = 0;
		u32 max_mixer_width;
		struct mdss_panel_info *pinfo;

		@@ -3120,6 +3120,16 @@ int mdss_mdp_ctl_setup(struct mdss_mdp_ctl *ctl)
		ctl->mixer_left->valid_roi = true;
		ctl->mixer_left->roi_changed = true;

		rc = mdss_mdp_pp_default_overlay_config(ctl->mfd, ctl->panel_data);
		/*
		* Ignore failure of PP config, ctl set-up can succeed.
		*/
		if (rc) {
		pr_err("failed to set the pp config rc %dfb %d\n", rc,
		ctl->mfd->index);
		rc = 0;
		}

		if (ctl->mfd->split_mode == MDP_DUAL_LM_DUAL_DISPLAY) {
		pr_debug("dual display detected\n");
		return 0;
		@@ -3162,7 +3172,6 @@ int mdss_mdp_ctl_setup(struct mdss_mdp_ctl *ctl)
		ctl->opmode &= ~(MDSS_MDP_CTL_OP_PACK_3D_ENABLE \|
		MDSS_MDP_CTL_OP_PACK_3D_H_ROW_INT);
		}

		return 0;
		}

drivers/video/msm/mdss/mdss_mdp_overlay.c

+0 −8

Original line number	Diff line number	Diff line
		@@ -4719,14 +4719,6 @@ static struct mdss_mdp_ctl *__mdss_mdp_overlay_ctl_init(
		}

		mdp5_data->ctl = ctl;

		rc = mdss_mdp_pp_default_overlay_config(mfd, pdata);
		if (rc) {
		pr_err("Unable to set default postprocessing configs for fb%d ret %d\n",
		mfd->index, rc);
		rc = 0;
		}

		error:
		if (rc)
		return ERR_PTR(rc);

drivers/video/msm/mdss/mdss_mdp_pp.c

+79 −7

Original line number	Diff line number	Diff line
		@@ -508,6 +508,7 @@ static int pp_mfd_release_all(struct msm_fb_data_type *mfd);
		static int pp_mfd_ad_release_all(struct msm_fb_data_type *mfd);
		static int mdss_mdp_ad_ipc_reset(struct msm_fb_data_type *mfd);
		static int pp_get_driver_ops(struct mdp_pp_driver_ops *ops);
		static int pp_ppb_setup(struct mdss_mdp_mixer *mixer);

		static u32 last_sts, last_state;

		@@ -2334,7 +2335,7 @@ static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_mixer *mixer)
		} else {
		addr = base + MDSS_MDP_REG_DSPP_DITHER_DEPTH;
		pp_ops[DITHER].pp_set_config(addr, pp_sts,
		&mdss_pp_res->dither_disp_cfg[disp_num], 0);
		&mdss_pp_res->dither_disp_cfg[disp_num], DSPP);
		}
		}
		if (flags & PP_FLAGS_DIRTY_GAMUT) {
		@@ -2508,10 +2509,12 @@ int mdss_mdp_pp_setup_locked(struct mdss_mdp_ctl *ctl)
		if (ctl->mixer_left) {
		pp_mixer_setup(ctl->mixer_left);
		pp_dspp_setup(disp_num, ctl->mixer_left);
		pp_ppb_setup(ctl->mixer_left);
		}
		if (ctl->mixer_right) {
		pp_mixer_setup(ctl->mixer_right);
		pp_dspp_setup(disp_num, ctl->mixer_right);
		pp_ppb_setup(ctl->mixer_right);
		}

		if (valid_mixers && (mixer_cnt <= mdata->nmax_concurrent_ad_hw) &&
		@@ -4274,20 +4277,38 @@ static int mdss_mdp_panel_default_dither_config(struct msm_fb_data_type *mfd,
		dither.version = dither_version.version_info;

		switch (panel_bpp) {
		case 24:
		dither.flags = MDP_PP_OPS_ENABLE \| MDP_PP_OPS_WRITE;
		switch (dither.version) {
		case mdp_dither_v1_7:
		dither_data.g_y_depth = 8;
		dither_data.r_cr_depth = 8;
		dither_data.b_cb_depth = 8;
		dither.cfg_payload = &dither_data;
		break;
		case mdp_pp_legacy:
		default:
		dither.g_y_depth = 8;
		dither.r_cr_depth = 8;
		dither.b_cb_depth = 8;
		dither.cfg_payload = NULL;
		break;
		}
		break;
		case 18:
		dither.flags = MDP_PP_OPS_ENABLE \| MDP_PP_OPS_WRITE;
		switch (dither.version) {
		case mdp_dither_v1_7:
		dither_data.g_y_depth = 2;
		dither_data.r_cr_depth = 2;
		dither_data.b_cb_depth = 2;
		dither_data.g_y_depth = 6;
		dither_data.r_cr_depth = 6;
		dither_data.b_cb_depth = 6;
		dither.cfg_payload = &dither_data;
		break;
		case mdp_pp_legacy:
		default:
		dither.g_y_depth = 2;
		dither.r_cr_depth = 2;
		dither.b_cb_depth = 2;
		dither.g_y_depth = 6;
		dither.r_cr_depth = 6;
		dither.b_cb_depth = 6;
		dither.cfg_payload = NULL;
		break;
		}
		@@ -7340,3 +7361,54 @@ static int pp_get_driver_ops(struct mdp_pp_driver_ops *ops)
		}
		return ret;
		}

		static int pp_ppb_setup(struct mdss_mdp_mixer *mixer)
		{
		struct pp_sts_type *pp_sts;
		struct mdss_mdp_ctl *ctl;
		char __iomem *addr;
		u32 flags, disp_num;
		int ret = 0;

		if (!mixer \|\| !mixer->ctl \|\| !mixer->ctl->mfd) {
		pr_err("invalid parameters, mixer %p ctl %p mfd %p\n",
		mixer, (mixer ? mixer->ctl : NULL),
		(mixer ? (mixer->ctl ? mixer->ctl->mfd : NULL) : NULL));
		return -EINVAL;
		}
		ctl = mixer->ctl;
		disp_num = ctl->mfd->index;

		if (disp_num < MDSS_BLOCK_DISP_NUM)
		flags = mdss_pp_res->pp_disp_flags[disp_num];
		else
		flags = 0;
		if ((flags & PP_FLAGS_DIRTY_DITHER)) {
		if (pp_ops[DITHER].pp_set_config) {
		pp_sts = &mdss_pp_res->pp_disp_sts[disp_num];
		addr = mixer->pingpong_base;
		/* if dither is supported in PPB function will
		* return 0. Failure will indicate that there
		* is no DITHER in PPB. In case of error skip the
		* programming of CTL flush bits for dither flush.
		* */
		ret = pp_ops[DITHER].pp_set_config(addr, pp_sts,
		&mdss_pp_res->dither_disp_cfg[disp_num], PPB);
		if (!ret) {
		switch (mixer->num) {
		case MDSS_MDP_INTF_LAYERMIXER0:
		case MDSS_MDP_INTF_LAYERMIXER1:
		case MDSS_MDP_INTF_LAYERMIXER2:
		ctl->flush_bits \|= BIT(13) <<
		mixer->num;
		break;
		case MDSS_MDP_INTF_LAYERMIXER3:
		ctl->flush_bits \|= BIT(21);
		break;
		}
		}
		ret = 0;
		}
		}
		return ret;
		}

drivers/video/msm/mdss/mdss_mdp_pp.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -84,7 +84,8 @@ enum pp_config_block {
		SSPP_DMA,
		SSPP_VIG,
		DSPP,
		LM
		LM,
		PPB
		};

		struct mdp_pp_feature_ops {

drivers/video/msm/mdss/mdss_mdp_pp_v1_7.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -539,7 +539,8 @@ static int pp_dither_set_config(char __iomem *base_addr,
		base_addr, cfg_data, pp_sts);
		return -EINVAL;
		}

		if (block_type != DSPP)
		return -ENOTSUPP;
		dither_cfg_data = (struct mdp_dither_cfg_data *) cfg_data;

		if (dither_cfg_data->version != mdp_dither_v1_7) {