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Commit a9963148 authored by Uwe Kleine-König's avatar Uwe Kleine-König
Browse files

ARM: imx: change static io mapping to use a function 



Now only the virtual addresses [0xf4000000, 0xf5ffffff] are used for
static per-SoC mappings.  The few mappings of whole chip selects are
moved accordingly.

The now wrong defines for virtual base addresses are removed.

Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
parent cf3a6aba

arch/arm/plat-mxc/include/mach/hardware.h

+67 −0
Original line number Diff line number Diff line
@@ -32,6 +32,73 @@ 
	(((addr) - module ## _BASE_ADDR) < module ## _SIZE ?		\

	 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)



/*

 * This is rather complicated for humans and ugly to verify, but for a machine

 * it's OK.  Still more as it is usually only applied to constants.  The upsides

 * on using this approach are:

 *

 *  - same mapping on all i.MX machines

 *  - works for assembler, too

 *  - no need to nurture #defines for virtual addresses

 *

 * The downside it, it's hard to verify (but I have a script for that).

 *

 * Obviously this needs to be injective for each SoC.  In general it maps the

 * whole address space to [0xf4000000, 0xf5ffffff].  So [0xf6000000,0xfeffffff]

 * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).

 *

 * It applies the following mappings for the different SoCs:

 *

 * mx1:

 *	IO	0x00200000+0x100000	->	0xf4000000+0x100000

 * mx21:

 *	AIPI	0x10000000+0x100000	->	0xf4400000+0x100000

 *	SAHB1	0x80000000+0x100000	->	0xf4000000+0x100000

 *	X_MEMC	0xdf000000+0x004000	->	0xf5f00000+0x004000

 * mx25:

 *	AIPS1	0x43f00000+0x100000	->	0xf5300000+0x100000

 *	AIPS2	0x53f00000+0x100000	->	0xf5700000+0x100000

 *	AVIC	0x68000000+0x100000	->	0xf5800000+0x100000

 * mx27:

 *	AIPI	0x10000000+0x100000	->	0xf4400000+0x100000

 *	SAHB1	0x80000000+0x100000	->	0xf4000000+0x100000

 *	X_MEMC	0xd8000000+0x100000	->	0xf5c00000+0x100000

 * mx31:

 *	AIPS1	0x43f00000+0x100000	->	0xf5300000+0x100000

 *	AIPS2	0x53f00000+0x100000	->	0xf5700000+0x100000

 *	AVIC	0x68000000+0x100000	->	0xf5800000+0x100000

 *	X_MEMC	0xb8000000+0x010000	->	0xf4c00000+0x010000

 *	SPBA0	0x50000000+0x100000	->	0xf5400000+0x100000

 * mx35:

 *	AIPS1	0x43f00000+0x100000	->	0xf5300000+0x100000

 *	AIPS2	0x53f00000+0x100000	->	0xf5700000+0x100000

 *	AVIC	0x68000000+0x100000	->	0xf5800000+0x100000

 *	X_MEMC	0xb8000000+0x010000	->	0xf4c00000+0x010000

 *	SPBA0	0x50000000+0x100000	->	0xf5400000+0x100000

 * mx51:

 *	IRAM	0x1ffe0000+0x020000	->	0xf4fe0000+0x020000

 *	DEBUG	0x60000000+0x100000	->	0xf5000000+0x100000

 *	SPBA0	0x70000000+0x100000	->	0xf5400000+0x100000

 *	AIPS1	0x73f00000+0x100000	->	0xf5700000+0x100000

 *	AIPS2	0x83f00000+0x100000	->	0xf4300000+0x100000

 * mxc91231:

 *	L2CC	0x30000000+0x010000	->	0xf4400000+0x010000

 *	X_MEMC	0xb8000000+0x010000	->	0xf4c00000+0x010000

 *	ROMP	0x60000000+0x010000	->	0xf5000000+0x010000

 *	AVIC	0x68000000+0x010000	->	0xf5800000+0x010000

 *	AIPS1	0x43f00000+0x100000	->	0xf5300000+0x100000

 *	SPBA0	0x50000000+0x100000	->	0xf5400000+0x100000

 *	SPBA1	0x52000000+0x100000	->	0xf5600000+0x100000

 *	AIPS2	0x53f00000+0x100000	->	0xf5700000+0x100000

 */

#define IMX_IO_P2V(x)	(						\

			0xf4000000 +					\

			(((x) & 0x50000000) >> 6) +			\

			(((x) & 0x0b000000) >> 4) +			\

			(((x) & 0x000fffff)))



#define IMX_IO_ADDRESS(x)	IOMEM(IMX_IO_P2V(x))



#ifdef CONFIG_ARCH_MX5

#include <mach/mx51.h>

#endif

arch/arm/plat-mxc/include/mach/mx1.h

+1 −4
Original line number Diff line number Diff line
@@ -19,7 +19,6 @@ 
 */

#define MX1_IO_BASE_ADDR	0x00200000

#define MX1_IO_SIZE		SZ_1M

#define MX1_IO_BASE_ADDR_VIRT	VMALLOC_END



#define MX1_CS0_PHYS		0x10000000

#define MX1_CS0_SIZE		0x02000000
@@ -73,8 +72,7 @@ 
#define MX1_CSI_BASE_ADDR		(0x24000 + MX1_IO_BASE_ADDR)



/* macro to get at IO space when running virtually */

#define MX1_IO_P2V(x)	(						\

	IMX_IO_P2V_MODULE(x, MX1_IO))

#define MX1_IO_P2V(x)			IMX_IO_P2V(x)

#define MX1_IO_ADDRESS(x)		IOMEM(MX1_IO_P2V(x))



/* fixed interrput numbers */
@@ -171,7 +169,6 @@ 
/* these should go away */

#define IMX_IO_PHYS MX1_IO_BASE_ADDR

#define IMX_IO_SIZE MX1_IO_SIZE

#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT

#define IMX_CS0_PHYS MX1_CS0_PHYS

#define IMX_CS0_SIZE MX1_CS0_SIZE

#define IMX_CS1_PHYS MX1_CS1_PHYS

arch/arm/plat-mxc/include/mach/mx21.h

+1 −8
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@ 
#define __MACH_MX21_H__



#define MX21_AIPI_BASE_ADDR		0x10000000

#define MX21_AIPI_BASE_ADDR_VIRT	0xf4000000

#define MX21_AIPI_SIZE			SZ_1M

#define MX21_DMA_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x01000)

#define MX21_WDOG_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x02000)
@@ -64,7 +63,6 @@ 
#define MX21_AVIC_BASE_ADDR		0x10040000



#define MX21_SAHB1_BASE_ADDR		0x80000000

#define MX21_SAHB1_BASE_ADDR_VIRT	0xf4100000

#define MX21_SAHB1_SIZE			SZ_1M

#define MX21_CSI_BASE_ADDR			(MX2x_SAHB1_BASE_ADDR + 0x0000)
@@ -82,7 +80,6 @@ 


/* NAND, SDRAM, WEIM etc controllers */

#define MX21_X_MEMC_BASE_ADDR		0xdf000000

#define MX21_X_MEMC_BASE_ADDR_VIRT	0xf4200000

#define MX21_X_MEMC_SIZE		SZ_256K



#define MX21_SDRAMC_BASE_ADDR		(MX21_X_MEMC_BASE_ADDR + 0x0000)
@@ -92,10 +89,7 @@ 


#define MX21_IRAM_BASE_ADDR		0xffffe800	/* internal ram */



#define MX21_IO_P2V(x)	(						\

	IMX_IO_P2V_MODULE(x, MX21_AIPI) ?:				\

	IMX_IO_P2V_MODULE(x, MX21_SAHB1) ?:				\

	IMX_IO_P2V_MODULE(x, MX21_X_MEMC))

#define MX21_IO_P2V(x)			IMX_IO_P2V(x)

#define MX21_IO_ADDRESS(x)		IOMEM(MX21_IO_P2V(x))



/* fixed interrupt numbers */
@@ -197,7 +191,6 @@ 
#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR

#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR

#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR

#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT

#define X_MEMC_SIZE MX21_X_MEMC_SIZE

#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR

#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR

arch/arm/plat-mxc/include/mach/mx25.h

+4 −9
Original line number Diff line number Diff line
@@ -2,13 +2,11 @@ 
#define __MACH_MX25_H__



#define MX25_AIPS1_BASE_ADDR		0x43f00000

#define MX25_AIPS1_BASE_ADDR_VIRT	0xfc000000

#define MX25_AIPS1_BASE_ADDR_VIRT	0xf5300000

#define MX25_AIPS1_SIZE			SZ_1M

#define MX25_AIPS2_BASE_ADDR		0x53f00000

#define MX25_AIPS2_BASE_ADDR_VIRT	0xfc200000

#define MX25_AIPS2_SIZE			SZ_1M

#define MX25_AVIC_BASE_ADDR		0x68000000

#define MX25_AVIC_BASE_ADDR_VIRT	0xfc400000

#define MX25_AVIC_SIZE			SZ_1M



#define MX25_I2C1_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0x80000)
@@ -27,12 +25,6 @@ 
#define MX25_GPIO2_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0xd0000)

#define MX25_WDOG_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0xdc000)



#define MX25_IO_P2V(x)	(					\

	IMX_IO_P2V_MODULE(x, MX25_AIPS1) ?:			\

	IMX_IO_P2V_MODULE(x, MX25_AIPS2) ?:			\

	IMX_IO_P2V_MODULE(x, MX25_AVIC))

#define MX25_IO_ADDRESS(x)		IOMEM(MX25_IO_P2V(x))



#define MX25_AIPS1_IO_ADDRESS(x) \

	(((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
@@ -58,6 +50,9 @@ 
#define MX25_OTG_BASE_ADDR		0x53ff4000

#define MX25_CSI_BASE_ADDR		0x53ff8000



#define MX25_IO_P2V(x)			IMX_IO_P2V(x)

#define MX25_IO_ADDRESS(x)		IOMEM(MX25_IO_P2V(x))



#define MX25_INT_CSPI3		0

#define MX25_INT_I2C1		3

#define MX25_INT_I2C2		4

arch/arm/plat-mxc/include/mach/mx27.h

+1 −8
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ 
#endif



#define MX27_AIPI_BASE_ADDR		0x10000000

#define MX27_AIPI_BASE_ADDR_VIRT	0xf4000000

#define MX27_AIPI_SIZE			SZ_1M

#define MX27_DMA_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x01000)

#define MX27_WDOG_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x02000)
@@ -87,7 +86,6 @@ 
#define MX27_ROMP_BASE_ADDR		0x10041000



#define MX27_SAHB1_BASE_ADDR		0x80000000

#define MX27_SAHB1_BASE_ADDR_VIRT	0xf4100000

#define MX27_SAHB1_SIZE			SZ_1M

#define MX27_CSI_BASE_ADDR			(MX27_SAHB1_BASE_ADDR + 0x0000)

#define MX27_ATA_BASE_ADDR			(MX27_SAHB1_BASE_ADDR + 0x1000)
@@ -105,7 +103,6 @@ 


/* NAND, SDRAM, WEIM, M3IF, EMI controllers */

#define MX27_X_MEMC_BASE_ADDR		0xd8000000

#define MX27_X_MEMC_BASE_ADDR_VIRT	0xf4200000

#define MX27_X_MEMC_SIZE		SZ_1M

#define MX27_NFC_BASE_ADDR			(MX27_X_MEMC_BASE_ADDR)

#define MX27_SDRAMC_BASE_ADDR			(MX27_X_MEMC_BASE_ADDR + 0x1000)
@@ -123,10 +120,7 @@ 
/* IRAM */

#define MX27_IRAM_BASE_ADDR		0xffff4c00	/* internal ram */



#define MX27_IO_P2V(x)	(						\

	IMX_IO_P2V_MODULE(x, MX27_AIPI) ?:				\

	IMX_IO_P2V_MODULE(x, MX27_SAHB1) ?:				\

	IMX_IO_P2V_MODULE(x, MX27_X_MEMC))

#define MX27_IO_P2V(x)			IMX_IO_P2V(x)

#define MX27_IO_ADDRESS(x)		IOMEM(MX27_IO_P2V(x))



#ifndef __ASSEMBLER__
@@ -280,7 +274,6 @@ extern int mx27_revision(void); 
#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR

#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR

#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR

#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT

#define X_MEMC_SIZE MX27_X_MEMC_SIZE

#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR

#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR