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Commit a96874a2 authored by Keng-Yu Lin's avatar Keng-Yu Lin Committed by Sarah Sharp
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Intel xhci: Only switch the switchable ports 



With a previous patch to enable the EHCI/XHCI port switching, it switches
all the available ports.

The assumption is not correct because the BIOS may expect some ports
not switchable by the OS.

There are two more registers that contains the information of the switchable
and non-switchable ports.

This patch adds the checking code for the two register so that only the
switchable ports are altered.

This patch should be backported to kernels as old as 3.0, that contain
commit ID 69e848c2 "Intel xhci: Support
EHCI/xHCI port switching."

Signed-off-by: default avatarKeng-Yu Lin <kengyu@canonical.com>
Signed-off-by: default avatarSarah Sharp <sarah.a.sharp@linux.intel.com>
Cc: stable@vger.kernel.org
parent 29d21457

drivers/usb/host/pci-quirks.c

+23 −4
Original line number Diff line number Diff line
@@ -75,7 +75,9 @@ 
#define	NB_PIF0_PWRDOWN_1	0x01100013



#define USB_INTEL_XUSB2PR      0xD0

#define USB_INTEL_USB2PRM      0xD4

#define USB_INTEL_USB3_PSSEN   0xD8

#define USB_INTEL_USB3PRM      0xDC



static struct amd_chipset_info {

	struct pci_dev	*nb_dev;
@@ -772,10 +774,18 @@ void usb_enable_xhci_ports(struct pci_dev *xhci_pdev) 
		return;

	}



	ports_available = 0xffffffff;

	/* Read USB3PRM, the USB 3.0 Port Routing Mask Register

	 * Indicate the ports that can be changed from OS.

	 */

	pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM,

			&ports_available);



	dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n",

			ports_available);



	/* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable

	 * Register, to turn on SuperSpeed terminations for all

	 * available ports.

	 * Register, to turn on SuperSpeed terminations for the

	 * switchable ports.

	 */

	pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,

			cpu_to_le32(ports_available));
@@ -785,7 +795,16 @@ void usb_enable_xhci_ports(struct pci_dev *xhci_pdev) 
	dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled "

			"under xHCI: 0x%x\n", ports_available);



	ports_available = 0xffffffff;

	/* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register

	 * Indicate the USB 2.0 ports to be controlled by the xHCI host.

	 */



	pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM,

			&ports_available);



	dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",

			ports_available);



	/* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to

	 * switch the USB 2.0 power and data lines over to the xHCI

	 * host.