Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a93cb29a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "One qxl 32-bit warning fix, the rest is a bunch of radeon fixes from
  Alex for some issues we've been seeing."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/qxl: fix build warnings on 32-bit
  radeon: use max_bus_speed to activate gen2 speeds
  drm/radeon: narrow scope of Apple re-POST hack
  drm/radeon: don't check crtcs in card_posted() on cards without DCE
  drm/radeon: fix card_posted check for newer asics
  drm/radeon: fix typo in cu_per_sh on verde
  drm/radeon: UVD block on SUMO2 is the same as on SUMO
parents 4203afc3 970fa986

drivers/gpu/drm/qxl/qxl_ioctl.c

+2 −2
Original line number Diff line number Diff line
@@ -151,7 +151,7 @@ static int qxl_execbuffer_ioctl(struct drm_device *dev, void *data, 
		struct qxl_bo *cmd_bo;

		int release_type;

		struct drm_qxl_command *commands =

			(struct drm_qxl_command *)execbuffer->commands;

			(struct drm_qxl_command *)(uintptr_t)execbuffer->commands;



		if (DRM_COPY_FROM_USER(&user_cmd, &commands[cmd_num],

				       sizeof(user_cmd)))
@@ -193,7 +193,7 @@ static int qxl_execbuffer_ioctl(struct drm_device *dev, void *data, 


		for (i = 0 ; i < user_cmd.relocs_num; ++i) {

			if (DRM_COPY_FROM_USER(&reloc,

					       &((struct drm_qxl_reloc *)user_cmd.relocs)[i],

					       &((struct drm_qxl_reloc *)(uintptr_t)user_cmd.relocs)[i],

					       sizeof(reloc))) {

				qxl_bo_list_unreserve(&reloc_list, true);

				qxl_release_unreserve(qdev, release);

drivers/gpu/drm/qxl/qxl_kms.c

+5 −4
Original line number Diff line number Diff line
@@ -128,12 +128,13 @@ int qxl_device_init(struct qxl_device *qdev, 


	qdev->vram_mapping = io_mapping_create_wc(qdev->vram_base, pci_resource_len(pdev, 0));

	qdev->surface_mapping = io_mapping_create_wc(qdev->surfaceram_base, qdev->surfaceram_size);

	DRM_DEBUG_KMS("qxl: vram %p-%p(%dM %dk), surface %p-%p(%dM %dk)\n",

		 (void *)qdev->vram_base, (void *)pci_resource_end(pdev, 0),

	DRM_DEBUG_KMS("qxl: vram %llx-%llx(%dM %dk), surface %llx-%llx(%dM %dk)\n",

		 (unsigned long long)qdev->vram_base,

		 (unsigned long long)pci_resource_end(pdev, 0),

		 (int)pci_resource_len(pdev, 0) / 1024 / 1024,

		 (int)pci_resource_len(pdev, 0) / 1024,

		 (void *)qdev->surfaceram_base,

		 (void *)pci_resource_end(pdev, 1),

		 (unsigned long long)qdev->surfaceram_base,

		 (unsigned long long)pci_resource_end(pdev, 1),

		 (int)qdev->surfaceram_size / 1024 / 1024,

		 (int)qdev->surfaceram_size / 1024);

drivers/gpu/drm/radeon/evergreen.c

+3 −7
Original line number Diff line number Diff line
@@ -4999,8 +4999,7 @@ void evergreen_fini(struct radeon_device *rdev) 


void evergreen_pcie_gen2_enable(struct radeon_device *rdev)

{

	u32 link_width_cntl, speed_cntl, mask;

	int ret;

	u32 link_width_cntl, speed_cntl;



	if (radeon_pcie_gen2 == 0)

		return;
@@ -5015,11 +5014,8 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev) 
	if (ASIC_IS_X2(rdev))

		return;



	ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);

	if (ret != 0)

		return;



	if (!(mask & DRM_PCIE_SPEED_50))

	if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&

		(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))

		return;



	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

drivers/gpu/drm/radeon/r600.c

+2 −7
Original line number Diff line number Diff line
@@ -4631,8 +4631,6 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) 
{

	u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;

	u16 link_cntl2;

	u32 mask;

	int ret;



	if (radeon_pcie_gen2 == 0)

		return;
@@ -4651,11 +4649,8 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) 
	if (rdev->family <= CHIP_R600)

		return;



	ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);

	if (ret != 0)

		return;



	if (!(mask & DRM_PCIE_SPEED_50))

	if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&

		(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))

		return;



	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

drivers/gpu/drm/radeon/radeon_device.c

+16 −11
Original line number Diff line number Diff line
@@ -467,23 +467,27 @@ bool radeon_card_posted(struct radeon_device *rdev) 
{

	uint32_t reg;



	/* required for EFI mode on macbook2,1 which uses an r5xx asic */

	if (efi_enabled(EFI_BOOT) &&

	    rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)

	    (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&

	    (rdev->family < CHIP_R600))

		return false;



	if (ASIC_IS_NODCE(rdev))

		goto check_memsize;



	/* first check CRTCs */

	if (ASIC_IS_DCE41(rdev)) {

	if (ASIC_IS_DCE4(rdev)) {

		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);

		if (reg & EVERGREEN_CRTC_MASTER_EN)

			return true;

	} else if (ASIC_IS_DCE4(rdev)) {

		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |

			if (rdev->num_crtc >= 4) {

				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);

			}

			if (rdev->num_crtc >= 6) {

				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |

					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);

			}

		if (reg & EVERGREEN_CRTC_MASTER_EN)

			return true;

	} else if (ASIC_IS_AVIVO(rdev)) {
@@ -500,6 +504,7 @@ bool radeon_card_posted(struct radeon_device *rdev) 
		}

	}



check_memsize:

	/* then check MEM_SIZE, in case the crtcs are off */

	if (rdev->family >= CHIP_R600)

		reg = RREG32(R600_CONFIG_MEMSIZE);