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Commit a87f5021 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add interrupt property support for SDX20"

parents 03368174 c249f9a8

Documentation/devicetree/bindings/mhi/msm_mhi_dev.txt

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ Optional property: 
		between host and device.

  - qcom,mhi-config-iatu: If property is present map the control and data region

		between host and device using iatu.

  - qcom,mhi-interrupt: If property is present register for mhi interrupt.

  - qcom,mhi-local-pa-base: The physical base address on the device used by the

		MHI device driver to map the control and data region with the

		MHI driver on the host. This property is required if iatu

Documentation/devicetree/bindings/pci/msm_ep_pcie.txt

+2 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ Optional Properties: 
  - qcom,pcie-active-config: boolean type; active configuration of PCIe

    addressing.

  - qcom,pcie-aggregated-irq: boolean type; interrupts are aggregated.

  - qcom,pcie-mhi-a7-irq: boolean type; MHI a7 has separate irq.

  - qcom,pcie-perst-enum: Link enumeration will be triggered by PERST

    deassertion.

  - mdm2apstatus-gpio: GPIO used by PCIe endpoint side to notify the host side.
@@ -117,6 +118,7 @@ Example: 
		qcom,pcie-link-speed = <1>;

		qcom,pcie-active-config;

		qcom,pcie-aggregated-irq;

		qcom,pcie-mhi-a7-irq;

		qcom,pcie-perst-enum;

		qcom,phy-status-reg = <0x728>;

		qcom,dbi-base-reg = <0x168>;

arch/arm/boot/dts/qcom/sdx20.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -353,6 +353,7 @@ 


	qcom,pcie-phy-ver = <5>;

	qcom,pcie-perst-enum;

	qcom,pcie-mhi-a7-irq;

	status = "disabled";

};
@@ -392,6 +393,7 @@ 
	interrupts = <0 119 0>;

	interrupt-names = "mhi-device-inta";

	qcom,mhi-ifc-id = <0x030317cb>;

	qcom,mhi-interrupt;

	status = "disabled";

};

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+1 −0
Original line number Diff line number Diff line
@@ -289,6 +289,7 @@ struct ep_pcie_dev_t { 
	u32                          link_speed;

	bool                         active_config;

	bool                         aggregated_irq;

	bool                         mhi_a7_irq;

	u32                          dbi_base_reg;

	u32                          slv_space_reg;

	u32                          phy_status_reg;

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+14 −3
Original line number Diff line number Diff line
@@ -600,9 +600,13 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) 
			BIT(EP_PCIE_INT_EVT_LINK_DOWN) |

			BIT(EP_PCIE_INT_EVT_BME) |

			BIT(EP_PCIE_INT_EVT_PM_TURNOFF) |

			BIT(EP_PCIE_INT_EVT_MHI_A7) |

			BIT(EP_PCIE_INT_EVT_DSTATE_CHANGE) |

			BIT(EP_PCIE_INT_EVT_LINK_UP));

		if (!dev->mhi_a7_irq)

			ep_pcie_write_mask(dev->parf +

				PCIE20_PARF_INT_ALL_MASK, 0,

				BIT(EP_PCIE_INT_EVT_MHI_A7));



		EP_PCIE_DBG(dev, "PCIe V%d: PCIE20_PARF_INT_ALL_MASK:0x%x\n",

			dev->rev,

			readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK));
@@ -1363,7 +1367,7 @@ int ep_pcie_core_mask_irq_event(enum ep_pcie_irq_event event, 
	spin_lock_irqsave(&dev->ext_lock, irqsave_flags);



	if (dev->aggregated_irq) {

		mask = readl_relaxed(dev->dm_core + PCIE20_PARF_INT_ALL_MASK);

		mask = readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK);

		EP_PCIE_DUMP(dev,

			"PCIe V%d: current PCIE20_PARF_INT_ALL_MASK:0x%x\n",

			dev->rev, mask);
@@ -1376,7 +1380,7 @@ int ep_pcie_core_mask_irq_event(enum ep_pcie_irq_event event, 
		EP_PCIE_DUMP(dev,

			"PCIe V%d: new PCIE20_PARF_INT_ALL_MASK:0x%x\n",

			dev->rev,

			readl_relaxed(dev->dm_core + PCIE20_PARF_INT_ALL_MASK));

			readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK));

	} else {

		EP_PCIE_ERR(dev,

			"PCIe V%d: Client askes to %s IRQ event 0x%x when aggregated IRQ is not supported.\n",
@@ -2286,6 +2290,13 @@ static int ep_pcie_probe(struct platform_device *pdev) 
		"PCIe V%d: aggregated IRQ is %s enabled.\n",

		ep_pcie_dev.rev, ep_pcie_dev.aggregated_irq ? "" : "not");



	ep_pcie_dev.mhi_a7_irq =

		of_property_read_bool((&pdev->dev)->of_node,

				"qcom,pcie-mhi-a7-irq");

	EP_PCIE_DBG(&ep_pcie_dev,

		"PCIe V%d: Mhi a7 IRQ is %s enabled.\n",

		ep_pcie_dev.rev, ep_pcie_dev.mhi_a7_irq ? "" : "not");



	ep_pcie_dev.perst_enum = of_property_read_bool((&pdev->dev)->of_node,

				"qcom,pcie-perst-enum");

	EP_PCIE_DBG(&ep_pcie_dev,