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Commit a7885aea authored by Sami Tolvanen's avatar Sami Tolvanen Committed by Amit Pundir
Browse files

Revert "FROMLIST: arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1" 



This reverts commit e68a0e26.

Bug: 31432001
Change-Id: Ibc242eb505b81522f07a5f63026de3e772575095
Signed-off-by: default avatarSami Tolvanen <samitolvanen@google.com>
parent becdc837

arch/arm64/include/asm/assembler.h

+0 −16
Original line number Diff line number Diff line
@@ -51,15 +51,6 @@ 
	msr	daifclr, #2

	.endm



	.macro	save_and_disable_irq, flags

	mrs	\flags, daif

	msr	daifset, #2

	.endm



	.macro	restore_irq, flags

	msr	daif, \flags

	.endm



/*

 * Save/disable and restore interrupts.

 */
@@ -305,11 +296,4 @@ lr .req x30 // link register 
9000:

	.endm



/*

 * Return the current thread_info.

 */

	.macro	get_thread_info, rd

	mrs	\rd, sp_el0

	.endm



#endif	/* __ASM_ASSEMBLER_H */

arch/arm64/include/asm/cpufeature.h

+0 −6
Original line number Diff line number Diff line
@@ -183,12 +183,6 @@ static inline bool system_supports_mixed_endian_el0(void) 
	return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));

}



static inline bool system_uses_ttbr0_pan(void)

{

	return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&

		!cpus_have_cap(ARM64_HAS_PAN);

}



#endif /* __ASSEMBLY__ */



#endif

arch/arm64/include/asm/kernel-pgtable.h

+0 −8
Original line number Diff line number Diff line
@@ -19,8 +19,6 @@ 
#ifndef __ASM_KERNEL_PGTABLE_H

#define __ASM_KERNEL_PGTABLE_H



#include <asm/pgtable.h>



/*

 * The idmap and swapper page tables need some space reserved in the kernel

 * image. Both require pgd, pud (4 levels only) and pmd tables to (section)
@@ -39,12 +37,6 @@ 
#define SWAPPER_DIR_SIZE	(SWAPPER_PGTABLE_LEVELS * PAGE_SIZE)

#define IDMAP_DIR_SIZE		(3 * PAGE_SIZE)



#ifdef CONFIG_ARM64_SW_TTBR0_PAN

#define RESERVED_TTBR0_SIZE	(PAGE_SIZE)

#else

#define RESERVED_TTBR0_SIZE	(0)

#endif



/* Initial memory map size */

#ifdef CONFIG_ARM64_64K_PAGES

#define SWAPPER_BLOCK_SHIFT	PAGE_SHIFT

arch/arm64/include/asm/thread_info.h

+0 −3
Original line number Diff line number Diff line
@@ -46,9 +46,6 @@ typedef unsigned long mm_segment_t; 
struct thread_info {

	unsigned long		flags;		/* low level flags */

	mm_segment_t		addr_limit;	/* address limit */

#ifdef CONFIG_ARM64_SW_TTBR0_PAN

	u64			ttbr0;		/* saved TTBR0_EL1 */

#endif

	struct task_struct	*task;		/* main task structure */

	struct exec_domain	*exec_domain;	/* execution domain */

	int			preempt_count;	/* 0 => preemptable, <0 => bug */

arch/arm64/include/asm/uaccess.h

+6 −91
Original line number Diff line number Diff line
@@ -28,7 +28,6 @@ 


#include <asm/alternative.h>

#include <asm/cpufeature.h>

#include <asm/kernel-pgtable.h>

#include <asm/ptrace.h>

#include <asm/sysreg.h>

#include <asm/errno.h>
@@ -121,55 +120,14 @@ static inline void set_fs(mm_segment_t fs) 
/*

 * User access enabling/disabling.

 */

#ifdef CONFIG_ARM64_SW_TTBR0_PAN

static inline void uaccess_ttbr0_disable(void)

{

	unsigned long ttbr;



	/* reserved_ttbr0 placed at the end of swapper_pg_dir */

	ttbr = read_sysreg(ttbr1_el1) + SWAPPER_DIR_SIZE;

	write_sysreg(ttbr, ttbr0_el1);

	isb();

}



static inline void uaccess_ttbr0_enable(void)

{

	unsigned long flags;



	/*

	 * Disable interrupts to avoid preemption between reading the 'ttbr0'

	 * variable and the MSR. A context switch could trigger an ASID

	 * roll-over and an update of 'ttbr0'.

	 */

	local_irq_save(flags);

	write_sysreg(current_thread_info()->ttbr0, ttbr0_el1);

	isb();

	local_irq_restore(flags);

}

#else

static inline void uaccess_ttbr0_disable(void)

{

}



static inline void uaccess_ttbr0_enable(void)

{

}

#endif



#define __uaccess_disable(alt)						\

do {									\

	if (system_uses_ttbr0_pan())					\

		uaccess_ttbr0_disable();				\

	else								\

	asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), alt,			\

			CONFIG_ARM64_PAN));				\

} while (0)



#define __uaccess_enable(alt)						\

do {									\

	if (system_uses_ttbr0_pan())					\

		uaccess_ttbr0_enable();					\

	else								\

	asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), alt,			\

			CONFIG_ARM64_PAN));				\

} while (0)
@@ -407,40 +365,12 @@ extern __must_check long strnlen_user(const char __user *str, long n); 


#include <asm/alternative.h>

#include <asm/assembler.h>

#include <asm/kernel-pgtable.h>

#include <asm/page.h>



/*

 * User access enabling/disabling macros.

 */

	.macro	uaccess_ttbr0_disable, tmp1

	mrs	\tmp1, ttbr1_el1		// swapper_pg_dir

	add	\tmp1, \tmp1, #SWAPPER_DIR_SIZE	// reserved_ttbr0 at the end of swapper_pg_dir

	msr	ttbr0_el1, \tmp1		// set reserved TTBR0_EL1

	isb

	.endm



	.macro	uaccess_ttbr0_enable, tmp1

	get_thread_info \tmp1

	ldr	\tmp1, [\tmp1, #TI_TTBR0]	// load saved TTBR0_EL1

	msr	ttbr0_el1, \tmp1		// set the non-PAN TTBR0_EL1

	isb

	.endm



/*

 * These macros are no-ops when UAO is present.

 * User access enabling/disabling macros. These are no-ops when UAO is

 * present.

 */

	.macro	uaccess_disable_not_uao, tmp1

#ifdef CONFIG_ARM64_SW_TTBR0_PAN

alternative_if_not ARM64_HAS_PAN

	uaccess_ttbr0_disable \tmp1

alternative_else

	nop

	nop

	nop

	nop

alternative_endif

#endif

alternative_if_not ARM64_ALT_PAN_NOT_UAO

	nop

alternative_else
@@ -449,21 +379,6 @@ alternative_endif 
	.endm



	.macro	uaccess_enable_not_uao, tmp1, tmp2

#ifdef CONFIG_ARM64_SW_TTBR0_PAN

alternative_if_not ARM64_HAS_PAN

	save_and_disable_irq \tmp2		// avoid preemption

	uaccess_ttbr0_enable \tmp1

	restore_irq \tmp2

alternative_else

	nop

	nop

	nop

	nop

	nop

	nop

	nop

alternative_endif

#endif

alternative_if_not ARM64_ALT_PAN_NOT_UAO

	nop

alternative_else