Loading arch/arm/boot/dts/qcom/msmtitanium-pinctrl.dtsi +49 −0 Original line number Diff line number Diff line Loading @@ -50,5 +50,54 @@ }; /* SDC pin type */ sdc1_clk_on: sdc1_clk_on { config { pins = "sdc1_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc1_clk_off: sdc1_clk_off { config { pins = "sdc1_clk"; bias-disable; /* NO pull */ drive-strength = <2>; /* 2 MA */ }; }; sdc1_cmd_on: sdc1_cmd_on { config { pins = "sdc1_cmd"; bias-pull-up; /* pull up */ drive-strength = <10>; /* 10 MA */ }; }; sdc1_cmd_off: sdc1_cmd_off { config { pins = "sdc1_cmd"; num-grp-pins = <1>; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; sdc1_data_on: sdc1_data_on { config { pins = "sdc1_data"; bias-pull-up; /* pull up */ drive-strength = <10>; /* 10 MA */ }; }; sdc1_data_off: sdc1_data_off { config { pins = "sdc1_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; }; }; arch/arm/boot/dts/qcom/msmtitanium-rumi.dts +23 −0 Original line number Diff line number Diff line Loading @@ -32,3 +32,26 @@ &blsp1_uart2 { status = "ok"; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pmtitanium_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pmtitanium_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; qcom,nonremovable; qcom,clk-rates = <400000 25000000 50000000>; status = "ok"; }; arch/arm/boot/dts/qcom/msmtitanium-sim.dts +23 −0 Original line number Diff line number Diff line Loading @@ -28,3 +28,26 @@ pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pmtitanium_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pmtitanium_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; qcom,nonremovable; qcom,clk-rates = <400000 25000000 50000000>; status = "ok"; }; arch/arm/boot/dts/qcom/msmtitanium.dtsi +37 −0 Original line number Diff line number Diff line Loading @@ -80,6 +80,7 @@ smd11 = &smdtty_data11; smd21 = &smdtty_data21; smd36 = &smdtty_loopback; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ }; soc: soc { }; Loading Loading @@ -411,6 +412,42 @@ qcom,xprt-version = <1>; qcom,fragmented-data; }; sdhc_1: sdhci@7824900 { compatible = "qcom,sdhci-msm"; reg = <0x7824900 0x500>, <0x7824000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <0 123 0>, <0 138 0>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <8>; qcom,devfreq,freq-table = <52000000 200000000>; qcom,cpu-dma-latency-us = <60 340 900>; qcom,msm-bus,name = "sdhc1"; qcom,msm-bus,num-cases = <9>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ <78 512 1046 3200>, /* 400 KB/s*/ <78 512 52286 160000>, /* 20 MB/s */ <78 512 65360 200000>, /* 25 MB/s */ <78 512 130718 400000>, /* 50 MB/s */ <78 512 130718 400000>, /* 100 MB/s */ <78 512 261438 800000>, /* 200 MB/s */ <78 512 261438 800000>, /* 400 MB/s */ <78 512 1338562 4096000>; /* Max. bandwidth */ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 400000000 4294967295>; clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>, <&clock_gcc clk_gcc_sdcc1_apps_clk>; clock-names = "iface_clk", "core_clk"; status = "disabled"; }; }; #include "msmtitanium-regulator.dtsi" Loading
arch/arm/boot/dts/qcom/msmtitanium-pinctrl.dtsi +49 −0 Original line number Diff line number Diff line Loading @@ -50,5 +50,54 @@ }; /* SDC pin type */ sdc1_clk_on: sdc1_clk_on { config { pins = "sdc1_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc1_clk_off: sdc1_clk_off { config { pins = "sdc1_clk"; bias-disable; /* NO pull */ drive-strength = <2>; /* 2 MA */ }; }; sdc1_cmd_on: sdc1_cmd_on { config { pins = "sdc1_cmd"; bias-pull-up; /* pull up */ drive-strength = <10>; /* 10 MA */ }; }; sdc1_cmd_off: sdc1_cmd_off { config { pins = "sdc1_cmd"; num-grp-pins = <1>; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; sdc1_data_on: sdc1_data_on { config { pins = "sdc1_data"; bias-pull-up; /* pull up */ drive-strength = <10>; /* 10 MA */ }; }; sdc1_data_off: sdc1_data_off { config { pins = "sdc1_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; }; };
arch/arm/boot/dts/qcom/msmtitanium-rumi.dts +23 −0 Original line number Diff line number Diff line Loading @@ -32,3 +32,26 @@ &blsp1_uart2 { status = "ok"; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pmtitanium_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pmtitanium_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; qcom,nonremovable; qcom,clk-rates = <400000 25000000 50000000>; status = "ok"; };
arch/arm/boot/dts/qcom/msmtitanium-sim.dts +23 −0 Original line number Diff line number Diff line Loading @@ -28,3 +28,26 @@ pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pmtitanium_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pmtitanium_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; qcom,nonremovable; qcom,clk-rates = <400000 25000000 50000000>; status = "ok"; };
arch/arm/boot/dts/qcom/msmtitanium.dtsi +37 −0 Original line number Diff line number Diff line Loading @@ -80,6 +80,7 @@ smd11 = &smdtty_data11; smd21 = &smdtty_data21; smd36 = &smdtty_loopback; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ }; soc: soc { }; Loading Loading @@ -411,6 +412,42 @@ qcom,xprt-version = <1>; qcom,fragmented-data; }; sdhc_1: sdhci@7824900 { compatible = "qcom,sdhci-msm"; reg = <0x7824900 0x500>, <0x7824000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <0 123 0>, <0 138 0>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <8>; qcom,devfreq,freq-table = <52000000 200000000>; qcom,cpu-dma-latency-us = <60 340 900>; qcom,msm-bus,name = "sdhc1"; qcom,msm-bus,num-cases = <9>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ <78 512 1046 3200>, /* 400 KB/s*/ <78 512 52286 160000>, /* 20 MB/s */ <78 512 65360 200000>, /* 25 MB/s */ <78 512 130718 400000>, /* 50 MB/s */ <78 512 130718 400000>, /* 100 MB/s */ <78 512 261438 800000>, /* 200 MB/s */ <78 512 261438 800000>, /* 400 MB/s */ <78 512 1338562 4096000>; /* Max. bandwidth */ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 400000000 4294967295>; clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>, <&clock_gcc clk_gcc_sdcc1_apps_clk>; clock-names = "iface_clk", "core_clk"; status = "disabled"; }; }; #include "msmtitanium-regulator.dtsi"