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Commit a6b963db authored by Krishna Gudipati's avatar Krishna Gudipati Committed by James Bottomley
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[SCSI] bfa: Flash controller IOC pll init fixes. 



Made changes to resume the flash controller if it is halted before going
ahead with flash controller pause/resume logic.
Made changes to avoid clearing off the interrupts during the initial
pll initialization.

Signed-off-by: default avatarKrishna Gudipati <kgudipat@brocade.com>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 8919678e

drivers/scsi/bfa/bfa_ioc_ct.c

+106 −45
Original line number Diff line number Diff line
@@ -786,42 +786,79 @@ bfa_ioc_ct2_mac_reset(void __iomem *rb) 
}



#define CT2_NFC_MAX_DELAY	1000

bfa_status_t

bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode)

#define CT2_NFC_VER_VALID	0x143

#define BFA_IOC_PLL_POLL	1000000



static bfa_boolean_t

bfa_ioc_ct2_nfc_halted(void __iomem *rb)

{

	u32	r32;



	r32 = readl(rb + CT2_NFC_CSR_SET_REG);

	if (r32 & __NFC_CONTROLLER_HALTED)

		return BFA_TRUE;



	return BFA_FALSE;

}



static void

bfa_ioc_ct2_nfc_resume(void __iomem *rb)

{

	u32	wgn, r32;

	u32	r32;

	int i;



	/*

	 * Initialize PLL if not already done by NFC

	 */

	wgn = readl(rb + CT2_WGN_STATUS);

	if (!(wgn & __GLBL_PF_VF_CFG_RDY)) {

		writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_SET_REG);

	writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_CLR_REG);

	for (i = 0; i < CT2_NFC_MAX_DELAY; i++) {

		r32 = readl(rb + CT2_NFC_CSR_SET_REG);

			if (r32 & __NFC_CONTROLLER_HALTED)

				break;

		if (!(r32 & __NFC_CONTROLLER_HALTED))

			return;

		udelay(1000);

	}

	WARN_ON(1);

}



	/*

	 * Mask the interrupts and clear any

	 * pending interrupts.

	 */

	writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK));

	writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK));

bfa_status_t

bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode)

{

	u32 wgn, r32, nfc_ver, i;



	r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));

	if (r32 == 1) {

		writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT));

		readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));

	wgn = readl(rb + CT2_WGN_STATUS);

	nfc_ver = readl(rb + CT2_RSC_GPR15_REG);



	if ((wgn == (__A2T_AHB_LOAD | __WGN_READY)) &&

	    (nfc_ver >= CT2_NFC_VER_VALID)) {

		if (bfa_ioc_ct2_nfc_halted(rb))

			bfa_ioc_ct2_nfc_resume(rb);



		writel(__RESET_AND_START_SCLK_LCLK_PLLS,

		       rb + CT2_CSI_FW_CTL_SET_REG);



		for (i = 0; i < BFA_IOC_PLL_POLL; i++) {

			r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);

			if (r32 & __RESET_AND_START_SCLK_LCLK_PLLS)

				break;

		}

	r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));

	if (r32 == 1) {

		writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT));

		readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));



		WARN_ON(!(r32 & __RESET_AND_START_SCLK_LCLK_PLLS));



		for (i = 0; i < BFA_IOC_PLL_POLL; i++) {

			r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);

			if (!(r32 & __RESET_AND_START_SCLK_LCLK_PLLS))

				break;

		}



		WARN_ON(r32 & __RESET_AND_START_SCLK_LCLK_PLLS);

		udelay(1000);



		r32 = readl(rb + CT2_CSI_FW_CTL_REG);

		WARN_ON(r32 & __RESET_AND_START_SCLK_LCLK_PLLS);

	} else {

		writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_SET_REG);

		for (i = 0; i < CT2_NFC_MAX_DELAY; i++) {

			r32 = readl(rb + CT2_NFC_CSR_SET_REG);

			if (r32 & __NFC_CONTROLLER_HALTED)

				break;

			udelay(1000);

		}



		bfa_ioc_ct2_mac_reset(rb);
@@ -831,30 +868,54 @@ bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode) 
		/*

		 * release soft reset on s_clk & l_clk

		 */

	r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

		r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);

		writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,

		       (rb + CT2_APP_PLL_SCLK_CTL_REG));



		/*

		 * release soft reset on s_clk & l_clk

		 */

	r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));

		r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);

		writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,

		      (rb + CT2_APP_PLL_LCLK_CTL_REG));

	}



	/*

	 * Announce flash device presence, if flash was corrupted.

	 */

	if (wgn == (__WGN_READY | __GLBL_PF_VF_CFG_RDY)) {

		r32 = readl((rb + PSS_GPIO_OUT_REG));

		r32 = readl(rb + PSS_GPIO_OUT_REG);

		writel(r32 & ~1, (rb + PSS_GPIO_OUT_REG));

		r32 = readl((rb + PSS_GPIO_OE_REG));

		r32 = readl(rb + PSS_GPIO_OE_REG);

		writel(r32 | 1, (rb + PSS_GPIO_OE_REG));

	}



	/*

	 * Mask the interrupts and clear any

	 * pending interrupts.

	 */

	writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK));

	writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK));



	/* For first time initialization, no need to clear interrupts */

	r32 = readl(rb + HOST_SEM5_REG);

	if (r32 & 0x1) {

		r32 = readl(rb + CT2_LPU0_HOSTFN_CMD_STAT);

		if (r32 == 1) {

			writel(1, rb + CT2_LPU0_HOSTFN_CMD_STAT);

			readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));

		}

		r32 = readl(rb + CT2_LPU1_HOSTFN_CMD_STAT);

		if (r32 == 1) {

			writel(1, rb + CT2_LPU1_HOSTFN_CMD_STAT);

			readl(rb + CT2_LPU1_HOSTFN_CMD_STAT);

		}

	}



	bfa_ioc_ct2_mem_init(rb);



	writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG));

	writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG));

	writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC0_STATE_REG);

	writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC1_STATE_REG);



	return BFA_STATUS_OK;

}

drivers/scsi/bfa/bfi_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -335,11 +335,17 @@ enum { 
#define __PMM_1T_PNDB_P			0x00000002

#define CT2_PMM_1T_CONTROL_REG_P1	0x00023c1c

#define CT2_WGN_STATUS			0x00014990

#define __A2T_AHB_LOAD			0x00000800

#define __WGN_READY			0x00000400

#define __GLBL_PF_VF_CFG_RDY		0x00000200

#define CT2_NFC_CSR_CLR_REG		0x00027420

#define CT2_NFC_CSR_SET_REG		0x00027424

#define __HALT_NFC_CONTROLLER		0x00000002

#define __NFC_CONTROLLER_HALTED		0x00001000

#define CT2_RSC_GPR15_REG		0x0002765c

#define CT2_CSI_FW_CTL_REG		0x00027080

#define CT2_CSI_FW_CTL_SET_REG		0x00027088

#define __RESET_AND_START_SCLK_LCLK_PLLS 0x00010000



#define CT2_CSI_MAC0_CONTROL_REG	0x000270d0

#define __CSI_MAC_RESET			0x00000010