Merge "iommu: Move away from gen_pool_alloc_aligned"

* Qualcomm MSM IOMMU v1

Required properties:

- compatible : one of:

	- "qcom,msm-smmu-v1"

	- "qcom,msm-smmu-v2"

	- "qcom,msm-mmu-500"

- reg : - offset and length of the register set for the device.

	- Optional offset and length for clock register for additional clock that

	needs to be turned on for access to this IOMMU.

	- Optional offset and length for enabling aggregated Context bank

	interrupts

- reg-names: "iommu_base", "clk_base" (optional), "smmu_local_base" (optional)

- label: name of this IOMMU instance.

Optional properties:

- qcom,iommu-secure-id : Secure identifier for the IOMMU block

- qcom,secure-context : boolean indicating that a context is secure and

  programmed by the secure environment.

- qcom,vdd-supply: Regulator needed to access IOMMU

- qcom,alt-vdd-supply : Alternative regulator needed to access IOMMU

  configuration registers.

- interrupts : Interrupt numbers for permormance and global fault interrupts

- interrupt-names: Refers to the interrupts number mentioned above.

	"pmon" : the performance monitor overflow interrupt number

	"global_cfg_NS_irq" : the global config non-secure interrupt number

	"global_client_NS_irq" : the global client non-secure interrupt number

	"global_cfg_S_irq" : the global config secure interrupt number

	"global_client_S_irq" : the global client secure interrupt number

- qcom,iommu-enable-halt : Enable halt of the IOMMU before programming certain	19

  registers

- qcom,iommu-pmu-ngroups: Number of Performance Monitor Unit (PMU) groups.

- qcom,iommu-pmu-ncounters: Number of PMU counters per group.

- qcom,iommu-pmu-event-classes: List of event classes supported.

- Bus scaling properties: See msm_bus.txt

- qcom,cb-base-offset: context bank 0's base address from global base address

- List of sub nodes, one for each of the translation context banks supported.

  Each sub node has the following required properties:

  - compatible : one of:

	- "qcom,msm-smmu-v1-ctx"

	- "qcom,msm-smmu-v2-ctx"

  - reg : offset and length of the register set for the context bank.

  - interrupts : should contain the context bank interrupt. If this is

    a secure context bank, this should be a list of 2 3-tuples where

    the first is the non-secure interrupt, and the second is the

    secure interrupt.

  - qcom,iommu-ctx-sids : List of stream identifiers associated with this

    translation context.

  - label : Name of the context bank

  - vdd-supply : vdd-supply: phandle to GDSC regulator controlling this IOMMU.

Optional properties:

- qcom,needs-alt-core-clk : boolean to enable the secondary core clock for

  access to the IOMMU configuration registers

- qcom,needs-alt-iface-clk : boolean to enable the secondary iface clock for

  access to the IOMMU configuration registers

- qcom,iommu-bfb-regs : An array of unsigned 32-bit integers corresponding to

  BFB register addresses that need to be configured for performance tuning

  purposes. If this property is present, the qcom,iommu-bfb-data must also be

  present. Register addresses are specified as an offset from the base of the

  IOMMU hardware block. This property may be omitted if no BFB register

  configuration needs to be done for a particular IOMMU hardware instance. The

  registers specified by this property shall fall within the IOMMU

  implementation-defined register region.

- qcom,iommu-bfb-data : An array of unsigned 32-bit integers representing the

  values to be programmed into the corresponding registers given by the

  qcom,iommu-bfb-regs property. If this property is present, the

  qcom,iommu-bfb-regs property shall also be present, and the lengths of both

  properties shall be the same.

- qcom,iommu-lpae-bfb-regs : See description for qcom,iommu-bfb-regs. This is

  the same property except this is for IOMMU with LPAE support.

- qcom,iommu-lpae-bfb-data : See description for qcom,iommu-bfb-data. This is

  the same property except this is for IOMMU with LPAE support.

- qcom,iommu-sid-mask : List of mask values to map the unique stream ids to

  the Stream Mapping Table entries.

Example:

	qcom,iommu@fda64000 {

		compatible = "qcom,msm-smmu-v1";

		reg = <0xfda64000 0x10000>;

		reg-names = "iommu_base";

		vdd-supply = <&gdsc_iommu>;

		qcom,iommu-bfb-regs = <0x204c 0x2050>;

		qcom,iommu-bfb-data = <0xffff 0xffce>;

		label = "iommu_0";

		qcom,iommu-pmu-ngroups = <1>;

		qcom,iommu-pmu-ncounters = <8>;

		qcom,iommu-pmu-event-classes = <0x00,

						0x01>;

		qcom,iommu-ctx@fda6c000 {

			compatible = "qcom,msm-smmu-v1-ctx";

			reg = <0xfda6c000 0x1000>;

			interrupts = <0 70 0>;

			qcom,iommu-ctx-sids = <0 2>;

			qcom,iommu-sid-mask = <0 0xf>;

			label = "ctx_0";

		};

		qcom,iommu-ctx@fda6d000 {

			compatible = "qcom,msm-smmu-v1-ctx";

			reg = <0xfda6d000 0x1000>;

			interrupts = <0 71 0>;

			qcom,iommu-ctx-sids = <1>;

			label = "ctx_1";

		};

	};

	  PAMU can authorize memory access, remap the memory address, and remap I/O

	  transaction types.

# MSM IOMMU support

config MSM_IOMMU

	bool "MSM IOMMU Support"

	select IOMMU_API

	select ARM_DMA_USE_IOMMU if ARM

	select ARM64_DMA_USE_IOMMU if ARM64

	help

	  Support for the IOMMUs found on certain Qualcomm SOCs.

	  These IOMMUs allow virtualization of the address space used by most

	  cores within the multimedia subsystem.

	  If unsure, say N here.

# MSM IOMMUv1 support

config MSM_IOMMU_V1

	bool "MSM IOMMUv1 Support"

	depends on ARCH_MSM8974 || ARCH_MSM8226 || ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8992 || ARCH_MSM8909

	select IOMMU_API

	select MSM_IOMMU

	help

	  Support for the IOMMUs (v1) found on certain Qualcomm SOCs.

	  These IOMMUs allow virtualization of the address space used by most

	  cores within the multimedia subsystem.

	  If unsure, say N here.

config MSM_IOMMU_PMON

	bool "MSM IOMMU Perfomance Monitoring Support"

	depends on (ARCH_MSM8974 || ARCH_MSM8610 || ARCH_MSM8226 || ARCH_APQ8084) && MSM_IOMMU

	help

	  Support for monitoring IOMMUs performance on certain Qualcomm SOCs.

	  It captures TLB statistics per context bank of the IOMMU as an

	  indication of its performance metric.

	  If unsure, say N here.

config IOMMU_PGTABLES_L2

	bool "Allow SMMU page tables in the L2 cache (Experimental)"

	depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n

	help

	  Improves TLB miss latency at the expense of potential L2 pollution.

	  However, with large multimedia buffers, the TLB should mostly contain

	  section mappings and TLB misses should be quite infrequent.

	  If unsure, say N here.

config IOMMU_LPAE

	bool "Enable support for LPAE in IOMMU"

	depends on MSM_IOMMU

	help

	  Enables Large Physical Address Extension (LPAE) for IOMMU. This allows

	  clients of IOMMU to access physical addresses that are greater than

	  32 bits.

	  If unsure, say N here.

config MSM_IOMMU_VBIF_CHECK

	bool "Enable support for VBIF check when IOMMU gets stuck"

	depends on MSM_IOMMU

	help

	  Enables an extra check in the IOMMU driver that logs debugging

	  information when TLB sync or iommu halt issue occurs. This helps

	  in debugging such issues.

	  If unsure, say N here.

config IOMMU_NON_SECURE

	bool "Turns on programming of secure SMMU by kernel"

	depends on MSM_IOMMU

        help

         Say Y here if you want the kernel to program all SMMUs regardless of

         whether SMMUs are secure or not. A secure SMMU is an SMMU that has

         its global address space programmed by the secure environment. In

         addition some of the context banks might be owned/programmed by the

         secure environment for a secure SMMU. Enabling this feature can be

         used during testing when the secure environment is not available

         and the kernel needs to program all the SMMUs.

         If unsure, say N here.

config IOMMU_FORCE_4K_MAPPINGS

	bool "Turns off mapping optimization and map only 4K pages"

	depends on MSM_IOMMU

        help

         Say Y here if you want the IOMMU driver to map buffers with

         4KB mapping only. With this, we don't get performance gains

         by optimizing mapping. This is a debug feature and should be

         used only when we want to profile the performance in the

         worst case scenario.

         If unsure, say N here.

# AMD IOMMU support

config AMD_IOMMU

	bool "AMD IOMMU support"

obj-$(CONFIG_IOMMU_IO_PGTABLE) += io-pgtable.o

obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o

obj-$(CONFIG_OF_IOMMU)	+= of_iommu.o

obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o msm_iommu_domains.o msm_iommu_mapping.o

obj-$(CONFIG_MSM_IOMMU_V1) += msm_iommu-v1.o msm_iommu_dev-v1.o msm_iommu_sec.o

obj-$(CONFIG_MSM_IOMMU_PMON) += msm_iommu_perfmon.o msm_iommu_perfmon-v1.o

ifdef CONFIG_IOMMU_LPAE

obj-$(CONFIG_MSM_IOMMU_V1) += msm_iommu_pagetable_lpae.o

else

obj-$(CONFIG_MSM_IOMMU_V1) += msm_iommu_pagetable.o

endif

obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o amd_iommu_init.o

obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o

obj-$(CONFIG_ARM_SMMU) += arm-smmu.o

}

EXPORT_SYMBOL_GPL(iommu_group_get);

/**

 * iommu_group_find - Find and return the group based on the group name.

 * Also increment the reference count.

 * @name: the name of the group

 *

 * This function is called by iommu drivers and clients to get the group

 * by the specified name.  If found, the group is returned and the group

 * reference is incremented, else NULL.

 */

struct iommu_group *iommu_group_find(const char *name)

{

	struct iommu_group *group;

	int next = 0;

	mutex_lock(&iommu_group_mutex);

	while ((group = idr_get_next(&iommu_group_ida.idr, &next))) {

		if (group->name) {

			if (strcmp(group->name, name) == 0)

				break;

		}

		++next;

	}

	mutex_unlock(&iommu_group_mutex);

	if (group)

		kobject_get(group->devices_kobj);

	return group;

}

EXPORT_SYMBOL_GPL(iommu_group_find);

/**

 * iommu_group_put - Decrement group reference

 * @group: the group to use

EXPORT_SYMBOL_GPL(default_iommu_map_sg);

/* DEPRECATED */

int iommu_map_range(struct iommu_domain *domain, unsigned int iova,

		    struct scatterlist *sg, unsigned int len, int opt)

int iommu_map_range(struct iommu_domain *domain, unsigned long iova,

		struct scatterlist *sg, size_t len, int prot)

{

	if (unlikely(domain->ops->map_range == NULL))

		return -ENODEV;

	BUG_ON(iova & (~PAGE_MASK));

	return domain->ops->map_range(domain, iova, sg, len, prot);

}

EXPORT_SYMBOL_GPL(iommu_map_range);

/* DEPRECATED */

int iommu_unmap_range(struct iommu_domain *domain, unsigned int iova,

		      unsigned int len)

int iommu_unmap_range(struct iommu_domain *domain, unsigned long iova,

		size_t len)

{

	if (unlikely(domain->ops->unmap_range == NULL))

		return -ENODEV;

	BUG_ON(iova & (~PAGE_MASK));

	return domain->ops->unmap_range(domain, iova, len);

}

EXPORT_SYMBOL_GPL(iommu_unmap_range);

int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr,

			       phys_addr_t paddr, u64 size, int prot)