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Commit a65d0862 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by H. Peter Anvin
Browse files

x86, mce: unify Intel thermal init 



Mechanic unification. No change in code.

[ Impact: cleanup, 32-bit / 64-bit unification ]

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent 6cc6f3eb

arch/x86/kernel/cpu/mcheck/Makefile

+2 −1
Original line number Diff line number Diff line 
obj-y				=  mce_$(BITS).o therm_throt.o



obj-$(CONFIG_X86_32)		+= k7.o p4.o p5.o p6.o winchip.o

obj-$(CONFIG_X86_MCE_INTEL)	+= mce_intel_64.o

obj-$(CONFIG_X86_MCE_P4THERMAL)	+= mce_intel.o

obj-$(CONFIG_X86_MCE_INTEL)	+= mce_intel_64.o mce_intel.o

obj-$(CONFIG_X86_MCE_AMD)	+= mce_amd_64.o

obj-$(CONFIG_X86_MCE_NONFATAL)	+= non-fatal.o

obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o

arch/x86/kernel/cpu/mcheck/mce.h

+11 −0
Original line number Diff line number Diff line 
#include <linux/init.h>

#include <asm/mce.h>



#ifdef CONFIG_X86_32



void amd_mcheck_init(struct cpuinfo_x86 *c);

void intel_p4_mcheck_init(struct cpuinfo_x86 *c);

void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
@@ -12,3 +14,12 @@ extern void (*machine_check_vector)(struct pt_regs *, long error_code); 


extern int nr_mce_banks;



void intel_set_thermal_handler(void);



#else



static inline void intel_set_thermal_handler(void) { }



#endif



void intel_init_thermal(struct cpuinfo_x86 *c);

arch/x86/kernel/cpu/mcheck/mce_intel.c

0 → 100644
+73 −0
Original line number Diff line number Diff line 
/*

 * Common code for Intel machine checks

 */

#include <linux/interrupt.h>

#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/init.h>

#include <linux/smp.h>



#include <asm/therm_throt.h>

#include <asm/processor.h>

#include <asm/system.h>

#include <asm/apic.h>

#include <asm/msr.h>



#include "mce.h"



void intel_init_thermal(struct cpuinfo_x86 *c)

{

	unsigned int cpu = smp_processor_id();

	int tm2 = 0;

	u32 l, h;



	/* Thermal monitoring depends on ACPI and clock modulation*/

	if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))

		return;



	/*

	 * First check if its enabled already, in which case there might

	 * be some SMM goo which handles it, so we can't even put a handler

	 * since it might be delivered via SMI already:

	 */

	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	h = apic_read(APIC_LVTTHMR);

	if ((l & (1 << 3)) && (h & APIC_DM_SMI)) {

		printk(KERN_DEBUG

		       "CPU%d: Thermal monitoring handled by SMI\n", cpu);

		return;

	}



	if (cpu_has(c, X86_FEATURE_TM2) && (l & (1 << 13)))

		tm2 = 1;



	/* Check whether a vector already exists */

	if (h & APIC_VECTOR_MASK) {

		printk(KERN_DEBUG

		       "CPU%d: Thermal LVT vector (%#x) already installed\n",

		       cpu, (h & APIC_VECTOR_MASK));

		return;

	}



	/* We'll mask the thermal vector in the lapic till we're ready: */

	h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;

	apic_write(APIC_LVTTHMR, h);



	rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);

	wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);



	intel_set_thermal_handler();



	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h);



	/* Unmask the thermal vector: */

	l = apic_read(APIC_LVTTHMR);

	apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);



	printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",

	       cpu, tm2 ? "TM2" : "TM1");



	/* enable thermal throttle processing */

	atomic_set(&therm_throt_en, 1);

}

arch/x86/kernel/cpu/mcheck/mce_intel_64.c

+2 −59
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ 
#include <asm/therm_throt.h>

#include <asm/apic.h>



#include "mce.h"



asmlinkage void smp_thermal_interrupt(void)

{

	__u64 msr_val;
@@ -34,65 +36,6 @@ asmlinkage void smp_thermal_interrupt(void) 
	irq_exit();

}



static inline void intel_set_thermal_handler(void) { }



static void intel_init_thermal(struct cpuinfo_x86 *c)

{

	unsigned int cpu = smp_processor_id();

	int tm2 = 0;

	u32 l, h;



	/* Thermal monitoring depends on ACPI and clock modulation*/

	if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))

		return;



	/*

	 * First check if its enabled already, in which case there might

	 * be some SMM goo which handles it, so we can't even put a handler

	 * since it might be delivered via SMI already:

	 */

	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	h = apic_read(APIC_LVTTHMR);

	if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {

		printk(KERN_DEBUG

		       "CPU%d: Thermal monitoring handled by SMI\n", cpu);

		return;

	}



	if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))

		tm2 = 1;



	/* Check whether a vector already exists */

	if (h & APIC_VECTOR_MASK) {

		printk(KERN_DEBUG

		       "CPU%d: Thermal LVT vector (%#x) already installed\n",

		       cpu, (h & APIC_VECTOR_MASK));

		return;

	}



	/* We'll mask the thermal vector in the lapic till we're ready: */

	h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;

	apic_write(APIC_LVTTHMR, h);



	rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);

	wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);



	intel_set_thermal_handler();



	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);



	/* Unmask the thermal vector: */

	l = apic_read(APIC_LVTTHMR);

	apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);



	printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",

	       cpu, tm2 ? "TM2" : "TM1");



	/* enable thermal throttle processing */

	atomic_set(&therm_throt_en, 1);

}



/*

 * Support for Intel Correct Machine Check Interrupts. This allows

 * the CPU to raise an interrupt when a corrected machine check happened.

arch/x86/kernel/cpu/mcheck/p4.c

+1 −58
Original line number Diff line number Diff line
@@ -66,68 +66,11 @@ void smp_thermal_interrupt(struct pt_regs *regs) 
	irq_exit();

}



static void intel_set_thermal_handler(void)

void intel_set_thermal_handler(void)

{

	vendor_thermal_interrupt = intel_thermal_interrupt;

}



/* P4/Xeon Thermal regulation detect and init: */

static void intel_init_thermal(struct cpuinfo_x86 *c)

{

	unsigned int cpu = smp_processor_id();

	int tm2 = 0;

	u32 l, h;



	/* Thermal monitoring depends on ACPI and clock modulation*/

	if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))

		return;



	/*

	 * First check if its enabled already, in which case there might

	 * be some SMM goo which handles it, so we can't even put a handler

	 * since it might be delivered via SMI already:

	 */

	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	h = apic_read(APIC_LVTTHMR);

	if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {

		printk(KERN_DEBUG

		       "CPU%d: Thermal monitoring handled by SMI\n", cpu);

		return;

	}



	if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))

		tm2 = 1;



	/* Check whether a vector already exists */

	if (h & APIC_VECTOR_MASK) {

		printk(KERN_DEBUG

		       "CPU%d: Thermal LVT vector (%#x) already installed\n",

		       cpu, (h & APIC_VECTOR_MASK));

		return;

	}



	/* We'll mask the thermal vector in the lapic till we're ready: */

	h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;

	apic_write(APIC_LVTTHMR, h);



	rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);

	wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);



	intel_set_thermal_handler();



	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);



	/* Unmask the thermal vector: */

	l = apic_read(APIC_LVTTHMR);

	apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);



	printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",

	       cpu, tm2 ? "TM2" : "TM1");



	/* enable thermal throttle processing */

	atomic_set(&therm_throt_en, 1);

}

#endif /* CONFIG_X86_MCE_P4THERMAL */



/* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */