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Commit a61dcb36 authored by shaoxing's avatar shaoxing Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add device tree for apq8009 robot-rome refboard 



In order to support apq8009 robot-rome platform, add this device
tree file. Subtype is 0x10, enable rome wifi configs.

Change-Id: I7260feb2cd1407ca8b9ddd8ec2fe618e3e286562
Signed-off-by: default avatarshaoxing <shaoxing@codeaurora.org>
parent c6b2aed4

arch/arm/boot/dts/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -326,6 +326,7 @@ dtb-$(CONFIG_ARCH_MSM8909) += msm8909-pm8916-mtp.dtb \ 
	apq8009-cdp-wcd9326-refboard.dtb \

	apq8009-rcm-wcd9326-refboard.dtb \

	apq8009-robot-refboard.dtb \

	apq8009-robot-rome.dtb \

	apq8009-mtp-drone.dtb \

	msm8909-mtp.dtb \

	msm8909-1gb-mtp.dtb

arch/arm/boot/dts/qcom/apq8009-robot-rome.dts

0 → 100644
+266 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/dts-v1/;



#include "msm8909-mtp.dtsi"

#include "msm8909-pm8916.dtsi"

#include "msm8909-pm8916-mtp.dtsi"



/ {

	model = "Qualcomm Technologies,Inc.APQ8009 Robot-Rome Reference Board";

	compatible = "qcom,apq8009-mtp", "qcom,apq8009", "qcom,mtp";

	qcom,msm-id = <265 2>,<245 2>;

	qcom,board-id= <8 0x10>;

};



&i2c_4 {

	smb1360_otg_supply: smb1360-chg-fg@14 {

		compatible = "qcom,smb1360-chg-fg";

		reg = <0x14>;

		interrupt-parent = <&msm_gpio>;

		interrupts = <58 8>;

		pinctrl-names = "default";

		pinctrl-0 = <&smb_int_default>;

		qcom,charging-disabled;

		qcom,empty-soc-disabled;

		qcom,chg-inhibit-disabled;

		qcom,float-voltage-mv = <4200>;

		qcom,iterm-ma = <200>;

		qcom,recharge-thresh-mv = <100>;

		qcom,thermal-mitigation = <1500 700 600 0>;

		regulator-name = "smb1360_otg_vreg";

	};

};



&i2c_1 {

	status = "disabled";

};



&i2c_2 {

	status = "disabled";

};



&i2c_5 {

	status = "disabled";

};



&spi_0 {

	status = "disabled";

};



&pm8916_chg {

	status = "ok";

	qcom,use-external-charger;

};



&pm8916_bms {

	status = "ok";

	qcom,disable-bms;

};



&usb_otg {

	interrupts = <0 134 0>,<0 140 0>,<0 136 0>;

	interrupt-names = "core_irq", "async_irq", "phy_irq";



	qcom,hsusb-otg-mode = <3>;

	vbus_otg-supply = <&smb1360_otg_supply>;

};



&msm_gpio {

	hsuart_active: default {

		mux {

			pins = "gpio20", "gpio21", "gpio111", "gpio112";

			function = "blsp_uart2";

		};



		config {

			pins = "gpio20", "gpio21", "gpio111", "gpio112";

			drive-strength = <16>;

			bias-disable;

		};

	};



	hsuart_sleep: sleep {

		mux {

			pins = "gpio20", "gpio21", "gpio111", "gpio112";

			function = "blsp_uart2";

		};



		config {

			pins = "gpio20", "gpio21", "gpio111", "gpio112";

			drive-strength = <2>;

			bias-disable;

		};

	};

};



&soc {

	blsp1_uart2_hs: uart@78b0000 {

		compatible = "qcom,msm-hsuart-v14";

		reg = <0x78b0000 0x200>,

			<0x7884000 0x1f000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp1_uart2_hs>;

		interrupts = <0 1 2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 108 0

				1 &intc 0 238 0

				2 &msm_gpio 21 0>;

		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xfd>;

		qcom,master-id = <86>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,

				<&clock_gcc clk_gcc_blsp1_ahb_clk>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&hsuart_sleep>;

		pinctrl-1 = <&hsuart_active>;

		qcom,bam-tx-ep-pipe-index = <2>;

		qcom,bam-rx-ep-pipe-index = <3>;

		qcom,msm-bus,name = "blsp1_uart2_hs";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<86 512 0 0>,

				<86 512 500 800>;

		status = "ok";

	};



	qcom,mcu_time_sync {

		compatible = "qcom,mcu-time-sync";

		qcom,mcu-link-gpio = <&msm_gpio 90 1>;

		status = "ok";

	};



	gpio_keys {

		status = "disabled";

	};



	cnss_sdio: qcom,cnss_sdio {

		compatible = "qcom,cnss_sdio";

		subsys-name = "AR6320";



		/**

		 * There is no vdd-wlan on board and this is not for DSRC.

		 * IO and XTAL share the same vreg.

		 */

		vdd-wlan-io-supply = <&pm8916_l5>;

		qcom,wlan-ramdump-dynamic = <0x200000>;

		qcom,msm-bus,name = "msm-cnss";

		qcom,msm-bus,num-cases = <4>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<79 512 0 0>,             /* No vote */

			<79 512 6250 200000>,     /* 50 Mbps */

			<79 512 25000 200000>,    /* 200 Mbps */

			<79 512 2048000 4096000>; /* MAX */

	};



	bluetooth: bt_qca6174 {

		compatible = "qca,qca6174";

		qca,bt-reset-gpio = <&msm_gpio 47 0>; /* BT_EN */

	};

};



&external_image_mem {

	reg = <0x0 0x87a00000>, <0x0 0x0600000>;

};



&modem_adsp_mem {

	reg = <0x0 0x88000000>, <0x0 0x01f00000>;

};



&peripheral_mem {

	reg = <0x0 0x89f00000>, <0x0 0x0700000>;

};



&msm_gpio {

	sdc2_wlan_gpio_on: sdc2_wlan_gpio_on {

		mux {

			pins = "gpio43";

			function = "gpio";

		};

		config {

			pins = "gpio43";

			drive-strength = <10>;

			bias-pull-up;

			output-high;

		};

	};



	sdc2_wlan_gpio_off: sdc2_wlan_gpio_off {

		mux {

			pins = "gpio43";

			function = "gpio";

		};

		config {

			pins = "gpio43";

			drive-strength = <2>;

			bias-disable;

			output-low;

		};

	};

};



&sdhc_2 {

	/delete-property/cd-gpios;

	#address-cells = <0>;

	interrupt-parent = <&sdhc_2>;

	interrupts = <0 1 2>;

	#interrupt-cells = <1>;

	interrupt-map-mask = <0xffffffff>;

	interrupt-map = <0 &intc 0 125 0

			1 &intc 0 221 0

			2 &msm_gpio 38 0>;

	interrupt-names = "hc_irq", "pwr_irq", "sdiowakeup_irq";



	qcom,vdd-voltage-level = <1800000 1800000>;

	qcom,vdd-current-level = <15000 400000>;



	qcom,vdd-io-voltage-level = <1800000 2950000>;

	qcom,vdd-io-current-level = <200 50000>;

	qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000

			50000000 100000000>;

	qcom,clk-rates = <400000 25000000 50000000 100000000>;

	qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";



	pinctrl-names = "active", "sleep";

	pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on

			&sdc2_wlan_gpio_on>;

	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;

	qcom,nonremovable;

	status = "ok";

};



&mdss_fb0 {

	status = "disabled";

	/delete-node/ qcom,cont-splash-memory;

};



&mdss_mdp {

	status = "disabled";

};



&mdss_dsi0_pll {

	status = "disabled";

};



&mdss_dsi0 {

	status = "disabled";

};



/delete-node/ &cont_splash_mem;