Loading drivers/net/wireless/b43/phy_n.c +18 −17 Original line number Diff line number Diff line Loading @@ -919,15 +919,15 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) B43_NPHY_C2_CGAINI_CL2DETECT); /* Set narrowband clip threshold */ b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); if (!dev->phy.is_40mhz) { /* Set dwell lengths */ b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); } /* Set wideband clip 2 threshold */ Loading @@ -949,7 +949,7 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); } b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); if (nphy->gain_boost) { if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && Loading @@ -970,8 +970,8 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT); b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); /* specs say about 2 loops, but wl does 4 */ for (i = 0; i < 4; i++) b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); Loading @@ -991,8 +991,8 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x74)); /* specs say about 2 loops, but wl does 4 */ for (i = 0; i < 4; i++) b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x74)); } Loading Loading @@ -1034,7 +1034,7 @@ static void b43_nphy_workarounds(struct b43_wldev *dev) u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) b43_nphy_classifier(dev, 1, 0); else b43_nphy_classifier(dev, 1, 1); Loading Loading @@ -3459,7 +3459,8 @@ static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) memset(nphy, 0, sizeof(*nphy)); //TODO init struct b43_phy_n /* wl goes path which is executed for gain_boost, assume it is true */ nphy->gain_boost = true; } static void b43_nphy_op_free(struct b43_wldev *dev) Loading Loading
drivers/net/wireless/b43/phy_n.c +18 −17 Original line number Diff line number Diff line Loading @@ -919,15 +919,15 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) B43_NPHY_C2_CGAINI_CL2DETECT); /* Set narrowband clip threshold */ b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); if (!dev->phy.is_40mhz) { /* Set dwell lengths */ b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); } /* Set wideband clip 2 threshold */ Loading @@ -949,7 +949,7 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); } b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); if (nphy->gain_boost) { if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && Loading @@ -970,8 +970,8 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT); b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); /* specs say about 2 loops, but wl does 4 */ for (i = 0; i < 4; i++) b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); Loading @@ -991,8 +991,8 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x74)); /* specs say about 2 loops, but wl does 4 */ for (i = 0; i < 4; i++) b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x74)); } Loading Loading @@ -1034,7 +1034,7 @@ static void b43_nphy_workarounds(struct b43_wldev *dev) u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) b43_nphy_classifier(dev, 1, 0); else b43_nphy_classifier(dev, 1, 1); Loading Loading @@ -3459,7 +3459,8 @@ static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) memset(nphy, 0, sizeof(*nphy)); //TODO init struct b43_phy_n /* wl goes path which is executed for gain_boost, assume it is true */ nphy->gain_boost = true; } static void b43_nphy_op_free(struct b43_wldev *dev) Loading