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Commit a50f2845 authored by Hareesh Gundu's avatar Hareesh Gundu Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Log clk set, enable and prepare failure 



Handle the clk API return value so that it’s easy
to catch un clocked GPU register access.

Change-Id: I5a1a9a6cbd673394f126bb17b849393268a22b1b
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: default avatarArchana Sriram <apsrir@codeaurora.org>
parent 0e3466e4

drivers/gpu/msm/kgsl_pwrctrl.c

+89 −29
Original line number Diff line number Diff line
@@ -82,7 +82,12 @@ static void kgsl_pwrctrl_set_state(struct kgsl_device *device, 
static void kgsl_pwrctrl_request_state(struct kgsl_device *device,

				unsigned int state);

static void kgsl_pwrctrl_retention_clk(struct kgsl_device *device, int state);



static int kgsl_pwrctrl_clk_set_rate(struct clk *grp_clk, unsigned int freq,

				const char *name);

static void _gpu_clk_prepare_enable(struct kgsl_device *device,

				struct clk *clk, const char *name);

static void _bimc_clk_prepare_enable(struct kgsl_device *device,

				struct clk *clk, const char *name);

/**

 * _record_pwrevent() - Record the history of the new event

 * @device: Pointer to the kgsl_device struct
@@ -385,7 +390,8 @@ void kgsl_pwrctrl_pwrlevel_change(struct kgsl_device *device, 
	pwrlevel = &pwr->pwrlevels[pwr->active_pwrlevel];

	/* Change register settings if any  BEFORE pwrlevel change*/

	kgsl_pwrctrl_pwrlevel_change_settings(device, 0);

	clk_set_rate(pwr->grp_clks[0], pwrlevel->gpu_freq);

	kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[0],

			pwrlevel->gpu_freq, clocks[0]);

	trace_kgsl_pwrlevel(device,

			pwr->active_pwrlevel, pwrlevel->gpu_freq,

			pwr->previous_pwrlevel,
@@ -401,9 +407,12 @@ void kgsl_pwrctrl_pwrlevel_change(struct kgsl_device *device, 
	if (pwr->gpu_bimc_int_clk) {

			if (pwr->active_pwrlevel == 0 &&

					!pwr->gpu_bimc_interface_enabled) {

				clk_set_rate(pwr->gpu_bimc_int_clk,

						pwr->gpu_bimc_int_clk_freq);

				clk_prepare_enable(pwr->gpu_bimc_int_clk);

				kgsl_pwrctrl_clk_set_rate(pwr->gpu_bimc_int_clk,

						pwr->gpu_bimc_int_clk_freq,

						"bimc_gpu_clk");

				_bimc_clk_prepare_enable(device,

						pwr->gpu_bimc_int_clk,

						"bimc_gpu_clk");

				pwr->gpu_bimc_interface_enabled = 1;

			} else if (pwr->previous_pwrlevel == 0

					&& pwr->gpu_bimc_interface_enabled) {
@@ -1626,10 +1635,10 @@ static void kgsl_pwrctrl_retention_clk(struct kgsl_device *device, int state) 
			&pwr->power_flags)) {

			trace_kgsl_retention_clk(device, state);

			/* prepare the mx clk to avoid RPM transactions*/

			clk_set_rate(pwr->dummy_mx_clk,

			kgsl_pwrctrl_clk_set_rate(pwr->dummy_mx_clk,

				pwr->pwrlevels

				[pwr->active_pwrlevel].

				gpu_freq);

				gpu_freq, "mx_clk");

			clk_prepare(pwr->dummy_mx_clk);

			/*

			 * Unprepare Gfx clocks to put Gfx rail to
@@ -1653,9 +1662,9 @@ static void kgsl_pwrctrl_retention_clk(struct kgsl_device *device, int state) 


			/* unprepare the dummy mx clk*/

			clk_unprepare(pwr->dummy_mx_clk);

			clk_set_rate(pwr->dummy_mx_clk,

			kgsl_pwrctrl_clk_set_rate(pwr->dummy_mx_clk,

				pwr->pwrlevels[pwr->num_pwrlevels - 1].

				gpu_freq);

				gpu_freq, "mx_clk");

		}

	}

}
@@ -1690,9 +1699,9 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state, 
						KGSL_STATE_DEEP_NAP)) {

				for (i = KGSL_MAX_CLKS - 1; i > 0; i--)

					clk_unprepare(pwr->grp_clks[i]);

				clk_set_rate(pwr->grp_clks[0],

				kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[0],

					pwr->pwrlevels[pwr->num_pwrlevels - 1].

					gpu_freq);

					gpu_freq, clocks[0]);

			}



			/* Turn off the IOMMU clocks */
@@ -1701,10 +1710,11 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state, 
			/* High latency clock maintenance. */

			for (i = KGSL_MAX_CLKS - 1; i > 0; i--)

				clk_unprepare(pwr->grp_clks[i]);

			if ((pwr->pwrlevels[0].gpu_freq > 0))

				clk_set_rate(pwr->grp_clks[0],

			if ((pwr->pwrlevels[0].gpu_freq > 0)) {

				kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[0],

					pwr->pwrlevels[pwr->num_pwrlevels - 1].

					gpu_freq);

					gpu_freq, clocks[0]);

			}

		}

	} else if (state == KGSL_PWRFLAGS_ON) {

		if (!test_and_set_bit(KGSL_PWRFLAGS_CLK_ON,
@@ -1715,25 +1725,28 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state, 
			if ((device->state != KGSL_STATE_NAP) &&

			(device->state != KGSL_STATE_DEEP_NAP)) {

				if (pwr->pwrlevels[0].gpu_freq > 0)

					clk_set_rate(pwr->grp_clks[0],

					kgsl_pwrctrl_clk_set_rate(

						pwr->grp_clks[0],

						pwr->pwrlevels

						[pwr->active_pwrlevel].

						gpu_freq);

				for (i = KGSL_MAX_CLKS - 1; i > 0; i--)

					clk_prepare(pwr->grp_clks[i]);

						gpu_freq, clocks[0]);

			}

			/* as last step, enable grp_clk

			   this is to let GPU interrupt to come */



			for (i = KGSL_MAX_CLKS - 1; i > 0; i--)

				clk_enable(pwr->grp_clks[i]);

				_gpu_clk_prepare_enable(device,

						pwr->grp_clks[i], clocks[i]);



			/* Enable the gpu-bimc-interface clocks */

			if (pwr->gpu_bimc_int_clk) {

				if (pwr->active_pwrlevel == 0 &&

					!pwr->gpu_bimc_interface_enabled) {

					clk_set_rate(pwr->gpu_bimc_int_clk,

						pwr->gpu_bimc_int_clk_freq);

					clk_prepare_enable(

						pwr->gpu_bimc_int_clk);

					kgsl_pwrctrl_clk_set_rate(

						pwr->gpu_bimc_int_clk,

						pwr->gpu_bimc_int_clk_freq,

						"bimc_gpu_clk");

					_bimc_clk_prepare_enable(device,

						pwr->gpu_bimc_int_clk,

						"bimc_gpu_clk");

					pwr->gpu_bimc_interface_enabled = 1;

				}

			}
@@ -2013,6 +2026,52 @@ static int _get_clocks(struct kgsl_device *device) 
	return 0;

}



/*

 * _gpu_clk_prepare_enable - Enable the specified GPU clock

 * Try once to enable it and then BUG() for debug

 */

static void _gpu_clk_prepare_enable(struct kgsl_device *device,

		struct clk *clk, const char *name)

{

	int ret;



	if (device->state == KGSL_STATE_NAP) {

		ret = clk_enable(clk);

		if (ret)

			goto err;

		return;

	}



	ret = clk_prepare_enable(clk);

	if (!ret)

		return;

err:

	/* Failure is fatal so BUG() to facilitate debug */

	KGSL_DRV_FATAL(device, "KGSL:%s enable error:%d\n", name, ret);

}



/*

 * _bimc_clk_prepare_enable - Enable the specified GPU clock

 *  Try once to enable it and then BUG() for debug

 */

static void _bimc_clk_prepare_enable(struct kgsl_device *device,

		struct clk *clk, const char *name)

{

	int ret = clk_prepare_enable(clk);

	/* Failure is fatal so BUG() to facilitate debug */

	if (ret)

		KGSL_DRV_FATAL(device, "KGSL:%s enable error:%d\n", name, ret);

}



static int kgsl_pwrctrl_clk_set_rate(struct clk *grp_clk, unsigned int freq,

		const char *name)

{

	int ret = clk_set_rate(grp_clk, freq);



	WARN(ret, "KGSL:%s set freq %d failed:%d\n", name, freq, ret);

	return ret;

}



int kgsl_pwrctrl_init(struct kgsl_device *device)

{

	int i, k, m, n = 0, result;
@@ -2087,11 +2146,12 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) 
		pwr->pwrlevels[i].gpu_freq = freq;

	}



	clk_set_rate(pwr->grp_clks[0],

		pwr->pwrlevels[pwr->num_pwrlevels - 1].gpu_freq);

	kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[0],

		pwr->pwrlevels[pwr->num_pwrlevels - 1].gpu_freq, clocks[0]);



	clk_set_rate(pwr->grp_clks[6],

		clk_round_rate(pwr->grp_clks[6], KGSL_RBBMTIMER_CLK_FREQ));

	kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[6],

		clk_round_rate(pwr->grp_clks[6], KGSL_RBBMTIMER_CLK_FREQ),

		clocks[6]);



	result = get_regulators(device);

	if (result)