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Commit a4e2b347 authored by Michael Chan's avatar Michael Chan Committed by Jeff Garzik
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[PATCH] tg3: add 5714/5715 support 



Add complete support for 5714/5715. These chips are very similar to
5780 so the changes are very trivial. A TG3_FLG2_5780_CLASS flag is
added to identify these chips.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarJeff Garzik <jgarzik@pobox.com>
parent 5fadd053

drivers/net/tg3.c

+25 −14
Original line number Diff line number Diff line
@@ -219,6 +219,10 @@ static struct pci_device_id tg3_pci_tbl[] = { 
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
@@ -570,7 +574,7 @@ static void tg3_switch_clocks(struct tg3 *tp) 
	u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);

	u32 orig_clock_ctrl;



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)

	if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)

		return;



	orig_clock_ctrl = clock_ctrl;
@@ -1210,7 +1214,7 @@ static int tg3_set_power_state(struct tg3 *tp, int state) 
		     CLOCK_CTRL_ALTCLK |

		     CLOCK_CTRL_PWRDOWN_PLL133);

		udelay(40);

	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {

	} else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {

		/* do nothing */

	} else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&

		     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
@@ -3712,14 +3716,14 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, 
	dev->mtu = new_mtu;



	if (new_mtu > ETH_DATA_LEN) {

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {

		if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {

			tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;

			ethtool_op_set_tso(dev, 0);

		}

		else

			tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;

	} else {

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)

		if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)

			tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;

		tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;

	}
@@ -3850,7 +3854,7 @@ static void tg3_init_rings(struct tg3 *tp) 
	memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);



	tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;

	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) &&

	if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&

	    (tp->dev->mtu > ETH_DATA_LEN))

		tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
@@ -4347,7 +4351,7 @@ static int tg3_chip_reset(struct tg3 *tp) 
	val &= ~PCIX_CAPS_RELAXED_ORDERING;

	pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {

	if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {

		u32 val;



		/* Chip reset on 5780 will reset MSI enable bit,
@@ -6003,7 +6007,7 @@ static int tg3_reset_hw(struct tg3 *tp) 
	tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);



	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&

	    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780))

	    !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))

		limit = 8;

	else

		limit = 16;
@@ -7237,7 +7241,7 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 
		cmd->supported |= (SUPPORTED_1000baseT_Half |

				   SUPPORTED_1000baseT_Full);



	if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))

	if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))

		cmd->supported |= (SUPPORTED_100baseT_Half |

				  SUPPORTED_100baseT_Full |

				  SUPPORTED_10baseT_Half |
@@ -8380,7 +8384,7 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp) 
	}



	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||

	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)) {

	    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {

		switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {

			case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:

				tp->nvram_jedecnum = JEDEC_ATMEL;
@@ -8980,7 +8984,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) 


		tp->phy_id = eeprom_phy_id;

		if (eeprom_phy_serdes) {

			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)

			if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)

				tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;

			else

				tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
@@ -9393,8 +9397,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
	}



	/* Find msi capability. */

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {

		tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;

		tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);

	}



	/* Initialize misc host control in PCI block. */

	tp->misc_host_ctrl |= (misc_ctrl_reg &
@@ -9412,7 +9419,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 


	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)

	    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))

		tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;



	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
@@ -9607,7 +9614,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
	 * ether_setup() via the alloc_etherdev() call

	 */

	if (tp->dev->mtu > ETH_DATA_LEN &&

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780)

	    !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))

		tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;



	/* Determine WakeOnLan speed to use. */
@@ -9830,7 +9837,7 @@ static int __devinit tg3_get_device_address(struct tg3 *tp) 
	mac_offset = 0x7c;

	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&

	     !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {

	    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {

		if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)

			mac_offset = 0xcc;

		if (tg3_nvram_lock(tp))
@@ -10148,6 +10155,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp) 
		} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {

			/* 5780 always in PCIX mode */

			tp->dma_rwctrl |= 0x00144000;

		} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {

			/* 5714 always in PCIX mode */

			tp->dma_rwctrl |= 0x00148000;

		} else {

			tp->dma_rwctrl |= 0x001b000f;

		}
@@ -10347,6 +10357,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp) 
	case PHY_ID_BCM5705:	return "5705";

	case PHY_ID_BCM5750:	return "5750";

	case PHY_ID_BCM5752:	return "5752";

	case PHY_ID_BCM5714:	return "5714";

	case PHY_ID_BCM5780:	return "5780";

	case PHY_ID_BCM8002:	return "8002/serdes";

	case 0:			return "serdes";

drivers/net/tg3.h

+9 −2
Original line number Diff line number Diff line
@@ -137,6 +137,7 @@ 
#define   ASIC_REV_5750			 0x04

#define   ASIC_REV_5752			 0x06

#define   ASIC_REV_5780			 0x08

#define   ASIC_REV_5714			 0x09

#define  GET_CHIP_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 8)

#define   CHIPREV_5700_AX		 0x70

#define   CHIPREV_5700_BX		 0x71
@@ -531,6 +532,8 @@ 
#define  MAC_SERDES_CFG_EDGE_SELECT	 0x00001000

#define MAC_SERDES_STAT			0x00000594

/* 0x598 --> 0x5b0 unused */

#define SERDES_RX_CTRL			0x000005b0	/* 5780/5714 only */

#define  SERDES_RX_SIG_DETECT		 0x00000400

#define SG_DIG_CTRL			0x000005b0

#define  SG_DIG_USING_HW_AUTONEG	 0x80000000

#define  SG_DIG_SOFT_RESET		 0x40000000
@@ -1329,6 +1332,8 @@ 
#define  GRC_LCLCTRL_CLEARINT		0x00000002

#define  GRC_LCLCTRL_SETINT		0x00000004

#define  GRC_LCLCTRL_INT_ON_ATTN	0x00000008

#define  GRC_LCLCTRL_USE_SIG_DETECT	0x00000010	/* 5714/5780 only */

#define  GRC_LCLCTRL_USE_EXT_SIG_DETECT	0x00000020	/* 5714/5780 only */

#define  GRC_LCLCTRL_GPIO_INPUT3	0x00000020

#define  GRC_LCLCTRL_GPIO_OE3		0x00000040

#define  GRC_LCLCTRL_GPIO_OUTPUT3	0x00000080
@@ -2175,6 +2180,7 @@ struct tg3 { 
					TG3_FLG2_MII_SERDES)

#define TG3_FLG2_PARALLEL_DETECT	0x01000000

#define TG3_FLG2_ICH_WORKAROUND		0x02000000

#define TG3_FLG2_5780_CLASS		0x04000000



	u32				split_mode_max_reqs;

#define SPLIT_MODE_5704_MAX_REQ		3
@@ -2222,6 +2228,7 @@ struct tg3 { 
#define PHY_ID_BCM5705			0x600081a0

#define PHY_ID_BCM5750			0x60008180

#define PHY_ID_BCM5752			0x60008100

#define PHY_ID_BCM5714			0x60008340

#define PHY_ID_BCM5780			0x60008350

#define PHY_ID_BCM8002			0x60010140

#define PHY_ID_INVALID			0xffffffff
@@ -2246,8 +2253,8 @@ struct tg3 { 
	 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \

	 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \

	 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \

	 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5780 || \

	 (X) == PHY_ID_BCM8002)

	 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \

	 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM8002)



	struct tg3_hw_stats		*hw_stats;

	dma_addr_t			stats_mapping;

include/linux/pci_ids.h

+2 −0
Original line number Diff line number Diff line
@@ -2165,11 +2165,13 @@ 
#define PCI_DEVICE_ID_TIGON3_5721	0x1659

#define PCI_DEVICE_ID_TIGON3_5705M	0x165d

#define PCI_DEVICE_ID_TIGON3_5705M_2	0x165e

#define PCI_DEVICE_ID_TIGON3_5714	0x1668

#define PCI_DEVICE_ID_TIGON3_5780	0x166a

#define PCI_DEVICE_ID_TIGON3_5780S	0x166b

#define PCI_DEVICE_ID_TIGON3_5705F	0x166e

#define PCI_DEVICE_ID_TIGON3_5750	0x1676

#define PCI_DEVICE_ID_TIGON3_5751	0x1677

#define PCI_DEVICE_ID_TIGON3_5715	0x1678

#define PCI_DEVICE_ID_TIGON3_5750M	0x167c

#define PCI_DEVICE_ID_TIGON3_5751M	0x167d

#define PCI_DEVICE_ID_TIGON3_5751F	0x167e