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Commit a4bd6a93 authored by Kumar Gala's avatar Kumar Gala Committed by Grant Likely
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powerpc/mm: Respect _PAGE_COHERENT on classic ppc32 SW 



Since we now set _PAGE_COHERENT in the Linux PTE we shouldn't be clearing
it out before we setup the SW TLB.  Today all the SW TLB machines
(603/e300) that we support are non-SMP, however there are some errata on
some devices that cause us to set _PAGE_COHERENT via CPU_FTR_NEED_COHERENT.

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
parent c9310920

arch/powerpc/kernel/head_32.S

+3 −3
Original line number Diff line number Diff line
@@ -511,7 +511,7 @@ InstructionTLBMiss: 
	and	r1,r1,r2		/* writable if _RW and _DIRTY */

	rlwimi	r3,r3,32-1,30,30	/* _PAGE_USER -> PP msb */

	rlwimi	r3,r3,32-1,31,31	/* _PAGE_USER -> PP lsb */

	ori	r1,r1,0xe14		/* clear out reserved bits and M */

	ori	r1,r1,0xe04		/* clear out reserved bits */

	andc	r1,r3,r1		/* PP = user? (rw&dirty? 2: 3): 0 */

	mtspr	SPRN_RPA,r1

	mfspr	r3,SPRN_IMISS
@@ -585,7 +585,7 @@ DataLoadTLBMiss: 
	and	r1,r1,r2		/* writable if _RW and _DIRTY */

	rlwimi	r3,r3,32-1,30,30	/* _PAGE_USER -> PP msb */

	rlwimi	r3,r3,32-1,31,31	/* _PAGE_USER -> PP lsb */

	ori	r1,r1,0xe14		/* clear out reserved bits and M */

	ori	r1,r1,0xe04		/* clear out reserved bits */

	andc	r1,r3,r1		/* PP = user? (rw&dirty? 2: 3): 0 */

	mtspr	SPRN_RPA,r1

	mfspr	r3,SPRN_DMISS
@@ -653,7 +653,7 @@ DataStoreTLBMiss: 
	stw	r3,0(r2)		/* update PTE (accessed/dirty bits) */

	/* Convert linux-style PTE to low word of PPC-style PTE */

	rlwimi	r3,r3,32-1,30,30	/* _PAGE_USER -> PP msb */

	li	r1,0xe15		/* clear out reserved bits and M */

	li	r1,0xe05		/* clear out reserved bits & PP lsb */

	andc	r1,r3,r1		/* PP = user? 2: 0 */

	mtspr	SPRN_RPA,r1

	mfspr	r3,SPRN_DMISS