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Commit a4459176 authored by Charan Teja Reddy's avatar Charan Teja Reddy
Browse files

ARM: dts: msm: add cpu cti for msmtitanium 



Add CPU CTI devices to the device tree.

Change-Id: I10fa55abefe0667885e7603c3aa75bbd912e9ed7
Signed-off-by: default avatarCharan Teja Reddy <charante@codeaurora.org>
parent bc851b4c

arch/arm/boot/dts/qcom/msmtitanium-coresight.dtsi

+122 −2
Original line number Diff line number Diff line
@@ -396,12 +396,132 @@ 
		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu0: cti@61b8000{

		compatible = "arm,coresight-cti";

		reg = <0x61b8000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <25>;

		coresight-name = "coresight-cti-cpu0";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU4>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu1: cti@61b9000{

		compatible = "arm,coresight-cti";

		reg = <0x61b9000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <26>;

		coresight-name = "coresight-cti-cpu1";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU5>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu2: cti@61ba000{

		compatible = "arm,coresight-cti";

		reg = <0x61ba000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <27>;

		coresight-name = "coresight-cti-cpu2";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU6>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu3: cti@61bb000{

		compatible = "arm,coresight-cti";

		reg = <0x61bb000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <28>;

		coresight-name = "coresight-cti-cpu3";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU7>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu4: cti@6198000{

		compatible = "arm,coresight-cti";

		reg = <0x6198000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <29>;

		coresight-name = "coresight-cti-cpu4";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu5: cti@6199000{

		compatible = "arm,coresight-cti";

		reg = <0x6199000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <30>;

		coresight-name = "coresight-cti-cpu5";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu6: cti@619a000{

		compatible = "arm,coresight-cti";

		reg = <0x619a000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <31>;

		coresight-name = "coresight-cti-cpu6";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu7: cti@619b000{

		compatible = "arm,coresight-cti";

		reg = <0x619b000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <32>;

		coresight-name = "coresight-cti-cpu7";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	csr: csr@6001000 {

		compatible = "qcom,coresight-csr";

		reg = <0x6001000 0x1000>;

		reg-names = "csr-base";



		coresight-id = <25>;

		coresight-id = <33>;

		coresight-name = "coresight-csr";

		coresight-nr-inports = <0>;

		qcom,blk-size = <1>;
@@ -416,7 +536,7 @@ 
		reg = <0x6108000 0x1000>;

		reg-names = "dbgui-base";



		coresight-id = <26>;

		coresight-id = <34>;

		coresight-name = "coresight-dbgui";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;