Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a3eb06db authored Jul 09, 2014 by Michel Dänzer Committed by Alex Deucher Aug 05, 2014

drm/radeon: Remove radeon_gart_restore()



Doesn't seem necessary, the GART table memory should be persistent.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 380670ae

drivers/gpu/drm/radeon/cik.c

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -5703,7 +5703,6 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
	r = radeon_gart_table_vram_pin(rdev);		r = radeon_gart_table_vram_pin(rdev);
	if (r)		if (r)
	return r;		return r;
	radeon_gart_restore(rdev);
	/* Setup TLB control */		/* Setup TLB control */
	WREG32(MC_VM_MX_L1_TLB_CNTL,		WREG32(MC_VM_MX_L1_TLB_CNTL,
	(0xA << 7) \|		(0xA << 7) \|

drivers/gpu/drm/radeon/evergreen.c

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -2424,7 +2424,6 @@ static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
	r = radeon_gart_table_vram_pin(rdev);		r = radeon_gart_table_vram_pin(rdev);
	if (r)		if (r)
	return r;		return r;
	radeon_gart_restore(rdev);
	/* Setup L2 cache */		/* Setup L2 cache */
	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|		WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|
	ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|

drivers/gpu/drm/radeon/ni.c

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1229,7 +1229,6 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
	r = radeon_gart_table_vram_pin(rdev);		r = radeon_gart_table_vram_pin(rdev);
	if (r)		if (r)
	return r;		return r;
	radeon_gart_restore(rdev);
	/* Setup TLB control */		/* Setup TLB control */
	WREG32(MC_VM_MX_L1_TLB_CNTL,		WREG32(MC_VM_MX_L1_TLB_CNTL,
	(0xA << 7) \|		(0xA << 7) \|

drivers/gpu/drm/radeon/r100.c

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -652,7 +652,6 @@ int r100_pci_gart_enable(struct radeon_device *rdev)
	{		{
	uint32_t tmp;		uint32_t tmp;

	radeon_gart_restore(rdev);
	/* discard memory request outside of configured range */		/* discard memory request outside of configured range */
	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;		tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
	WREG32(RADEON_AIC_CNTL, tmp);		WREG32(RADEON_AIC_CNTL, tmp);

drivers/gpu/drm/radeon/r300.c

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -120,7 +120,6 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
	r = radeon_gart_table_vram_pin(rdev);		r = radeon_gart_table_vram_pin(rdev);
	if (r)		if (r)
	return r;		return r;
	radeon_gart_restore(rdev);
	/* discard memory request outside of configured range */		/* discard memory request outside of configured range */
	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;		tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);