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Commit a3b181f7 authored by Meng Wang's avatar Meng Wang Committed by Gerrit - the friendly Code Review server
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ASoc: codecs: Add digital codec driver for msm8909w 



MSM8909w wtp device has digital codec only. Current
codec driver has both analog and digital codec
driver mixed. Add digital codec driver for msm8909w
wtp device.

Change-Id: I392971e35f97b55fb34a68a89031beedc821393c
Signed-off-by: default avatarMeng Wang <mwang@codeaurora.org>
parent 8cf945f5

Documentation/devicetree/bindings/sound/qcom-audio-dev.txt

+27 −0
Original line number Diff line number Diff line
@@ -2785,3 +2785,30 @@ Example: 
                        qcom,msm-glink-channels = <4>;

                };

        };



* Digital Codec Driver.



Required properties:

- compatible : "qcom,msm-digital-codec"

- reg : This property provides the digital codec register address.

- cdc-vdd-digit-supply : Power supply that controls dmic and external

  speaker.

- qcom,cdc-vdd-digit-voltage : dmic and external speaker supply's voltage

  level in mV

- qcom,cdc-vdd-digit-current : dmic and external speaker max current level

  in mA

- qcom,cdc-on-demand-supplies : List of supplies which can be enabled

  dynamically. Supplies in this list are off by default.





Example:



	msm_digital_codec: msm-dig-codec@771c000 {

		compatible = "qcom,msm-digital-codec";

		reg = <0x0771c000 0x0>;



		cdc-vdd-digital-supply = <&pm660_l11>;

		qcom,cdc-vdd-digital-voltage = <1800000 1800000>;

		qcom,cdc-vdd-digital-current = <5000>;

		qcom,cdc-on-demand-supplies = "cdc-vdd-digital";

	};

sound/soc/codecs/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -652,6 +652,10 @@ config SND_SOC_WSA881X_ANALOG 
config SND_SOC_MSM8X16_WCD

	tristate



config SND_SOC_DIGITAL_CDC

	tristate

	select REGMAP_MMIO



config SND_SOC_WCD9XXX

	tristate

	default y if SND_SOC_WCD9320=y || SND_SOC_WCD9330=y || SND_SOC_WCD9335=y

sound/soc/codecs/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -126,6 +126,7 @@ snd-soc-wsa881x-objs := wsa881x.o wsa881x-tables.o wsa881x-regmap.o 
snd-soc-wsa881x-sensor-objs := wsa881x-temp-sensor.o

snd-soc-wcd-mbhc-objs := wcd-mbhc-v2.o

snd-soc-msm8952-wcd-objs := msm8x16-wcd.o msm8x16-wcd-tables.o

snd-soc-msm8909-cdc-objs := msm-digital-cdc.o msm-digital-cdc-regmap.o

snd-soc-wsa881x-analog-objs := wsa881x-analog.o wsa881x-tables-analog.o

snd-soc-wsa881x-analog-objs += wsa881x-regmap-analog.o wsa881x-irq.o

snd-soc-wl1273-objs := wl1273.o
@@ -315,6 +316,7 @@ obj-$(CONFIG_AUDIO_EXT_CLK) += audio-ext-clock.o 
obj-$(CONFIG_SND_SOC_WCD9XXX)   += snd-soc-wcd9xxx.o

obj-$(CONFIG_SND_SOC_WCD9XXX_V2) += snd-soc-wcd9xxx-v2.o

obj-$(CONFIG_SND_SOC_MSM8X16_WCD)	+= snd-soc-msm8952-wcd.o msm8916-wcd-irq.o

obj-$(CONFIG_SND_SOC_DIGITAL_CDC) += snd-soc-msm8909-cdc.o msm8916-wcd-irq.o

obj-$(CONFIG_SND_SOC_WCD_CPE)   += snd-soc-wcd-cpe.o

obj-$(CONFIG_SND_SOC_WCD_MBHC)  += snd-soc-wcd-mbhc.o

obj-$(CONFIG_SND_SOC_WSA881X)	+= snd-soc-wsa881x.o

sound/soc/codecs/msm-digital-cdc-registers.h

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+131 −0
Original line number Diff line number Diff line 
 /* Copyright (c) 2015-2016, 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#ifndef DIGITAL_CDC_REGISTERS_H

#define DIGITAL_CDC_REGISTERS_H



#define MSM89XX_CDC_CORE_CLK_RX_RESET_CTL	(0x00)

#define MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL	(0x04)

#define MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL	(0x08)

#define MSM89XX_CDC_CORE_CLK_RX_I2S_CTL		(0x0C)

#define MSM89XX_CDC_CORE_CLK_TX_I2S_CTL		(0x10)

#define MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL	(0x14)

#define MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL	(0x18)

#define MSM89XX_CDC_CORE_CLK_OTHR_CTL		(0x1C)

#define MSM89XX_CDC_CORE_CLK_RX_B1_CTL		(0x20)

#define MSM89XX_CDC_CORE_CLK_MCLK_CTL		(0x24)

#define MSM89XX_CDC_CORE_CLK_PDM_CTL		(0x28)

#define MSM89XX_CDC_CORE_CLK_SD_CTL		(0x2C)

#define MSM89XX_CDC_CORE_RX1_B1_CTL		(0x40)

#define MSM89XX_CDC_CORE_RX2_B1_CTL		(0x60)

#define MSM89XX_CDC_CORE_RX3_B1_CTL		(0x80)

#define MSM89XX_CDC_CORE_RX1_B2_CTL		(0x44)

#define MSM89XX_CDC_CORE_RX2_B2_CTL		(0x64)

#define MSM89XX_CDC_CORE_RX3_B2_CTL		(0x84)

#define MSM89XX_CDC_CORE_RX1_B3_CTL		(0x48)

#define MSM89XX_CDC_CORE_RX2_B3_CTL		(0x68)

#define MSM89XX_CDC_CORE_RX3_B3_CTL		(0x88)

#define MSM89XX_CDC_CORE_RX1_B4_CTL		(0x4C)

#define MSM89XX_CDC_CORE_RX2_B4_CTL		(0x6C)

#define MSM89XX_CDC_CORE_RX3_B4_CTL		(0x8C)

#define MSM89XX_CDC_CORE_RX1_B5_CTL		(0x50)

#define MSM89XX_CDC_CORE_RX2_B5_CTL		(0x70)

#define MSM89XX_CDC_CORE_RX3_B5_CTL		(0x90)

#define MSM89XX_CDC_CORE_RX1_B6_CTL		(0x54)

#define MSM89XX_CDC_CORE_RX2_B6_CTL		(0x74)

#define MSM89XX_CDC_CORE_RX3_B6_CTL		(0x94)

#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL	(0x58)

#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL	(0x78)

#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL	(0x98)

#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL	(0x5C)

#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL	(0x7C)

#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL	(0x9C)

#define MSM89XX_CDC_CORE_TOP_GAIN_UPDATE	(0xA0)

#define MSM89XX_CDC_CORE_TOP_CTL		(0xA4)

#define MSM89XX_CDC_CORE_DEBUG_DESER1_CTL	(0xE0)

#define MSM89XX_CDC_CORE_DEBUG_DESER2_CTL	(0xE4)

#define MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG	(0xE8)

#define MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG	(0xEC)

#define MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG	(0xF0)

#define MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL	(0x100)

#define MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL	(0x140)

#define MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL	(0x104)

#define MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL	(0x144)

#define MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL	(0x108)

#define MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL	(0x148)

#define MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL	(0x10C)

#define MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL	(0x14C)

#define MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL	(0x110)

#define MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL	(0x150)

#define MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL	(0x114)

#define MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL	(0x154)

#define MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL	(0x118)

#define MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL	(0x158)

#define MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL	(0x11C)

#define MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL	(0x15C)

#define MSM89XX_CDC_CORE_IIR1_CTL		(0x120)

#define MSM89XX_CDC_CORE_IIR2_CTL		(0x160)

#define MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL	(0x124)

#define MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL	(0x164)

#define MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL	(0x128)

#define MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL	(0x168)

#define MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL	(0x12C)

#define MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL	(0x16C)

#define MSM89XX_CDC_CORE_CONN_RX1_B1_CTL	(0x180)

#define MSM89XX_CDC_CORE_CONN_RX1_B2_CTL	(0x184)

#define MSM89XX_CDC_CORE_CONN_RX1_B3_CTL	(0x188)

#define MSM89XX_CDC_CORE_CONN_RX2_B1_CTL	(0x18C)

#define MSM89XX_CDC_CORE_CONN_RX2_B2_CTL	(0x190)

#define MSM89XX_CDC_CORE_CONN_RX2_B3_CTL	(0x194)

#define MSM89XX_CDC_CORE_CONN_RX3_B1_CTL	(0x198)

#define MSM89XX_CDC_CORE_CONN_RX3_B2_CTL	(0x19C)

#define MSM89XX_CDC_CORE_CONN_TX_B1_CTL		(0x1A0)

#define MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL	(0x1A8)

#define MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL	(0x1AC)

#define MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL	(0x1B0)

#define MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL	(0x1B4)

#define MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL	(0x1B8)

#define MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL	(0x1BC)

#define MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL	(0x1C0)

#define MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL	(0x1C4)

#define MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL	(0x1C8)

#define MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER	(0x280)

#define MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER	(0x2A0)

#define MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER	(0x2C0)

#define MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER	(0x2E0)

#define MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN	(0x284)

#define MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN	(0x2A4)

#define MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN	(0x2C4)

#define MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN	(0x2E4)

#define MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG	(0x288)

#define MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG	(0x2A8)

#define MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG	(0x2C8)

#define MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG	(0x2E8)

#define MSM89XX_CDC_CORE_TX1_MUX_CTL		(0x28C)

#define MSM89XX_CDC_CORE_TX2_MUX_CTL		(0x2AC)

#define MSM89XX_CDC_CORE_TX3_MUX_CTL		(0x2CC)

#define MSM89XX_CDC_CORE_TX4_MUX_CTL		(0x2EC)

#define MSM89XX_CDC_CORE_TX1_CLK_FS_CTL		(0x290)

#define MSM89XX_CDC_CORE_TX2_CLK_FS_CTL		(0x2B0)

#define MSM89XX_CDC_CORE_TX3_CLK_FS_CTL		(0x2D0)

#define MSM89XX_CDC_CORE_TX4_CLK_FS_CTL		(0x2F0)

#define MSM89XX_CDC_CORE_TX1_DMIC_CTL		(0x294)

#define MSM89XX_CDC_CORE_TX2_DMIC_CTL		(0x2B4)

#define MSM89XX_CDC_CORE_TX3_DMIC_CTL		(0x2D4)

#define MSM89XX_CDC_CORE_TX4_DMIC_CTL		(0x2F4)



#define MSM89XX_CDC_CORE_NUM_REGISTERS \

		(MSM89XX_CDC_CORE_TX4_DMIC_CTL+1)

#define MSM89XX_CDC_CORE_MAX_REGISTER \

		(MSM89XX_CDC_CORE_NUM_REGISTERS-1)

#define MSM89XX_CDC_CORE_CACHE_SIZE \

		MSM89XX_CDC_CORE_NUM_REGISTERS

#endif

sound/soc/codecs/msm-digital-cdc-regmap.c

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+390 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <linux/regmap.h>

#include "msm-digital-cdc.h"

#include "msm-digital-cdc-registers.h"



/*

 * Default register reset values that are common across different versions

 * are defined here. If a register reset value is changed based on version

 * then remove it from this structure and add it in version specific

 * structures.

 */

struct reg_default

	msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE] = {

	{MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, 0x00},

	{MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x13},

	{MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 0x13},

	{MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_CLK_OTHR_CTL, 0x04},

	{MSM89XX_CDC_CORE_CLK_RX_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x00},

	{MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x00},

	{MSM89XX_CDC_CORE_CLK_SD_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX1_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX2_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX3_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX1_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX2_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX3_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX1_B3_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX2_B3_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX3_B3_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX1_B4_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX2_B4_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX3_B4_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX1_B5_CTL, 0x68},

	{MSM89XX_CDC_CORE_RX2_B5_CTL, 0x68},

	{MSM89XX_CDC_CORE_RX3_B5_CTL, 0x68},

	{MSM89XX_CDC_CORE_RX1_B6_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX2_B6_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX3_B6_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_TOP_GAIN_UPDATE, 0x00},

	{MSM89XX_CDC_CORE_TOP_CTL, 0x01},

	{MSM89XX_CDC_CORE_DEBUG_DESER1_CTL, 0x00},

	{MSM89XX_CDC_CORE_DEBUG_DESER2_CTL, 0x00},

	{MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG, 0x00},

	{MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG, 0x00},

	{MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG, 0x00},

	{MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR1_CTL, 0x40},

	{MSM89XX_CDC_CORE_IIR2_CTL, 0x40},

	{MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_RX2_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_RX3_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_TX_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL, 0x00},

	{MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL, 0x00},

	{MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER, 0x00},

	{MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER, 0x00},

	{MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER, 0x00},

	{MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER, 0x00},

	{MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, 0x00},

	{MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, 0x00},

	{MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, 0x00},

	{MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, 0x00},

	{MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG, 0x00},

	{MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG, 0x00},

	{MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG, 0x00},

	{MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG, 0x00},

	{MSM89XX_CDC_CORE_TX1_MUX_CTL, 0x00},

	{MSM89XX_CDC_CORE_TX2_MUX_CTL, 0x00},

	{MSM89XX_CDC_CORE_TX3_MUX_CTL, 0x00},

	{MSM89XX_CDC_CORE_TX4_MUX_CTL, 0x00},

	{MSM89XX_CDC_CORE_TX1_CLK_FS_CTL, 0x03},

	{MSM89XX_CDC_CORE_TX2_CLK_FS_CTL, 0x03},

	{MSM89XX_CDC_CORE_TX3_CLK_FS_CTL, 0x03},

	{MSM89XX_CDC_CORE_TX4_CLK_FS_CTL, 0x03},

	{MSM89XX_CDC_CORE_TX1_DMIC_CTL, 0x00},

	{MSM89XX_CDC_CORE_TX2_DMIC_CTL, 0x00},

	{MSM89XX_CDC_CORE_TX3_DMIC_CTL, 0x00},

	{MSM89XX_CDC_CORE_TX4_DMIC_CTL, 0x00},

};



static const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE] = {

		[MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_SD_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_B5_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_B5_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_B5_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_B6_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_B6_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_B6_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1,

		[MSM89XX_CDC_CORE_TOP_CTL] = 1,

		[MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1,

		[MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1,

		[MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1,

		[MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1,

		[MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1,

		[MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1,

		[MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1,

		[MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1,

		[MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1,

		[MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1,

		[MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1,

		[MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1,

		[MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1,

		[MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1,

		[MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1,

		[MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1,

		[MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1,

		[MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1,

		[MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1,

		[MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1,

		[MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1,

		[MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1,

		[MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1,

};



static const u8 msm89xx_cdc_core_reg_writeable[MSM89XX_CDC_CORE_CACHE_SIZE] = {

		[MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1,

		[MSM89XX_CDC_CORE_CLK_SD_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_B5_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_B5_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_B5_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_B6_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_B6_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_B6_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1,

		[MSM89XX_CDC_CORE_TOP_CTL] = 1,

		[MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1,

		[MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1,

		[MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1,

		[MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1,

		[MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1,

		[MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1,

		[MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1,

		[MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1,

		[MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1,

		[MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1,

		[MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1,

		[MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1,

		[MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1,

		[MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1,

		[MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1,

		[MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1,

		[MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1,

		[MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1,

		[MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1,

		[MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1,

		[MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1,

		[MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1,

		[MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1,

		[MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1,

		[MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1,

};



bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg)

{

	return msm89xx_cdc_core_reg_readable[reg];

}



bool msm89xx_cdc_core_writeable_reg(struct device *dev, unsigned int reg)

{

	return msm89xx_cdc_core_reg_writeable[reg];

}



bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg)

{

	switch (reg) {

	case MSM89XX_CDC_CORE_RX1_B1_CTL:

	case MSM89XX_CDC_CORE_RX2_B1_CTL:

	case MSM89XX_CDC_CORE_RX3_B1_CTL:

	case MSM89XX_CDC_CORE_RX1_B6_CTL:

	case MSM89XX_CDC_CORE_RX2_B6_CTL:

	case MSM89XX_CDC_CORE_RX3_B6_CTL:

	case MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG:

	case MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG:

	case MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG:

	case MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG:

	case MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL:

	case MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL:

	case MSM89XX_CDC_CORE_CLK_MCLK_CTL:

	case MSM89XX_CDC_CORE_CLK_PDM_CTL:

		return true;

	default:

		return false;

	}

}