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Commit a3a80544 authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Will Deacon
Browse files

arm64: fix typo in I-cache policy detection 



This removes an unfortunately placed semi-colon resulting in all instruction
caches being classified as AIVIVT.

Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 7d1311b9

arch/arm64/kernel/cpuinfo.c

+1 −1
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 


	if (l1ip != ICACHE_POLICY_PIPT)

		set_bit(ICACHEF_ALIASING, &__icache_flags);

	if (l1ip == ICACHE_POLICY_AIVIVT);

	if (l1ip == ICACHE_POLICY_AIVIVT)

		set_bit(ICACHEF_AIVIVT, &__icache_flags);



	pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);