Loading arch/arm/boot/dts/qcom/msm8996-regulator.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -762,7 +762,7 @@ 1036800000 1113600000 1190400000 1248000000 1324800000 1401600000 1478400000 1555200000 1632000000 1708800000 1785600000 1826400000 1708800000 1785600000 1824000000 1920000000 1996800000 2073600000 2150400000>; Loading arch/arm/boot/dts/qcom/msm8996-v3.dtsi +27 −5 Original line number Diff line number Diff line Loading @@ -273,7 +273,11 @@ < 1036800000 9 >, < 1113600000 10 >, < 1190400000 11 >, < 1228800000 12 >; < 1228800000 12 >, < 1324800000 13 >, < 1401600000 14 >, < 1478400000 15 >, < 1593600000 16 >; qcom,perfcl-speedbin0-v0 = < 0 0 >, < 307200000 1 >, Loading @@ -288,7 +292,19 @@ < 1036800000 10 >, < 1113600000 11 >, < 1190400000 12 >, < 1248000000 13 >; < 1248000000 13 >, < 1324800000 14 >, < 1401600000 15 >, < 1478400000 16 >, < 1555200000 17 >, < 1632000000 18 >, < 1708800000 19 >, < 1785600000 20 >, < 1824000000 21 >, < 1920000000 22 >, < 1996800000 23 >, < 2073600000 24 >, < 2150400000 25 >; qcom,cbf-speedbin0-v0 = < 0 0 >, < 307200000 1 >, Loading @@ -303,7 +319,13 @@ < 979200000 10 >, < 1056000000 11 >, < 1132800000 12 >, < 1190400000 13 >; < 1190400000 13 >, < 1228800000 14 >, < 1305600000 15 >, < 1382400000 16 >, < 1459200000 17 >, < 1536000000 18 >, < 1593600000 19 >; }; &msm_cpufreq { Loading Loading @@ -345,7 +367,7 @@ < 1632000 >, < 1708800 >, < 1785600 >, < 1826400 >, < 1824000 >, < 1920000 >, < 1996800 >, < 2073600 >, Loading Loading @@ -413,7 +435,7 @@ < 1632000 1382400 >, < 1708800 1382400 >, < 1785600 1459200 >, < 1826400 1459200 >, < 1824000 1459200 >, < 1920000 1536000 >, < 1996800 1593600 >, < 2073600 1593600 >, Loading drivers/clk/msm/clock-cpu-8996.c +1 −1 Original line number Diff line number Diff line Loading @@ -181,7 +181,7 @@ static struct alpha_pll_vco_tbl alt_pll_vco_modes[] = { VCO(3, 250000000, 500000000), VCO(2, 500000000, 750000000), VCO(1, 750000000, 1000000000), VCO(0, 1000000000, 2000000000), VCO(0, 1000000000, 2150400000), }; static struct alpha_pll_clk perfcl_alt_pll = { Loading Loading
arch/arm/boot/dts/qcom/msm8996-regulator.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -762,7 +762,7 @@ 1036800000 1113600000 1190400000 1248000000 1324800000 1401600000 1478400000 1555200000 1632000000 1708800000 1785600000 1826400000 1708800000 1785600000 1824000000 1920000000 1996800000 2073600000 2150400000>; Loading
arch/arm/boot/dts/qcom/msm8996-v3.dtsi +27 −5 Original line number Diff line number Diff line Loading @@ -273,7 +273,11 @@ < 1036800000 9 >, < 1113600000 10 >, < 1190400000 11 >, < 1228800000 12 >; < 1228800000 12 >, < 1324800000 13 >, < 1401600000 14 >, < 1478400000 15 >, < 1593600000 16 >; qcom,perfcl-speedbin0-v0 = < 0 0 >, < 307200000 1 >, Loading @@ -288,7 +292,19 @@ < 1036800000 10 >, < 1113600000 11 >, < 1190400000 12 >, < 1248000000 13 >; < 1248000000 13 >, < 1324800000 14 >, < 1401600000 15 >, < 1478400000 16 >, < 1555200000 17 >, < 1632000000 18 >, < 1708800000 19 >, < 1785600000 20 >, < 1824000000 21 >, < 1920000000 22 >, < 1996800000 23 >, < 2073600000 24 >, < 2150400000 25 >; qcom,cbf-speedbin0-v0 = < 0 0 >, < 307200000 1 >, Loading @@ -303,7 +319,13 @@ < 979200000 10 >, < 1056000000 11 >, < 1132800000 12 >, < 1190400000 13 >; < 1190400000 13 >, < 1228800000 14 >, < 1305600000 15 >, < 1382400000 16 >, < 1459200000 17 >, < 1536000000 18 >, < 1593600000 19 >; }; &msm_cpufreq { Loading Loading @@ -345,7 +367,7 @@ < 1632000 >, < 1708800 >, < 1785600 >, < 1826400 >, < 1824000 >, < 1920000 >, < 1996800 >, < 2073600 >, Loading Loading @@ -413,7 +435,7 @@ < 1632000 1382400 >, < 1708800 1382400 >, < 1785600 1459200 >, < 1826400 1459200 >, < 1824000 1459200 >, < 1920000 1536000 >, < 1996800 1593600 >, < 2073600 1593600 >, Loading
drivers/clk/msm/clock-cpu-8996.c +1 −1 Original line number Diff line number Diff line Loading @@ -181,7 +181,7 @@ static struct alpha_pll_vco_tbl alt_pll_vco_modes[] = { VCO(3, 250000000, 500000000), VCO(2, 500000000, 750000000), VCO(1, 750000000, 1000000000), VCO(0, 1000000000, 2000000000), VCO(0, 1000000000, 2150400000), }; static struct alpha_pll_clk perfcl_alt_pll = { Loading