Loading arch/arm64/kernel/cpu_errata.c +7 −0 Original line number Diff line number Diff line Loading @@ -23,6 +23,7 @@ #define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) #define MIDR_KRYO2XX_SILVER MIDR_CPU_PART(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER) #define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ MIDR_ARCHITECTURE_MASK) Loading Loading @@ -81,6 +82,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_WORKAROUND_845719, MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), }, { /* Kryo2xx Silver rAp4 */ .desc = "Kryo2xx Silver erratum 845719", .capability = ARM64_WORKAROUND_845719, MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA00004, 0xA00004), }, #endif { } Loading Loading
arch/arm64/kernel/cpu_errata.c +7 −0 Original line number Diff line number Diff line Loading @@ -23,6 +23,7 @@ #define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) #define MIDR_KRYO2XX_SILVER MIDR_CPU_PART(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER) #define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ MIDR_ARCHITECTURE_MASK) Loading Loading @@ -81,6 +82,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_WORKAROUND_845719, MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), }, { /* Kryo2xx Silver rAp4 */ .desc = "Kryo2xx Silver erratum 845719", .capability = ARM64_WORKAROUND_845719, MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA00004, 0xA00004), }, #endif { } Loading