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Commit a2757b6f authored by Zhenyu Wang's avatar Zhenyu Wang Committed by Eric Anholt
Browse files

agp/intel: Add actual definitions of the Sandybridge PTE caching bits.

parent 3869d4a8

drivers/char/agp/intel-agp.h

+6 −0
Original line number Original line Diff line number Diff line
@@ -60,6 +60,12 @@ 
#define I810_PTE_LOCAL		0x00000002

#define I810_PTE_LOCAL		0x00000002

#define I810_PTE_VALID		0x00000001

#define I810_PTE_VALID		0x00000001

#define I830_PTE_SYSTEM_CACHED  0x00000006

#define I830_PTE_SYSTEM_CACHED  0x00000006

/* GT PTE cache control fields */

#define GEN6_PTE_UNCACHED	0x00000002

#define GEN6_PTE_LLC		0x00000004

#define GEN6_PTE_LLC_MLC	0x00000006

#define GEN6_PTE_GFDT		0x00000008



#define I810_SMRAM_MISCC	0x70

#define I810_SMRAM_MISCC	0x70

#define I810_GFX_MEM_WIN_SIZE	0x00010000

#define I810_GFX_MEM_WIN_SIZE	0x00010000

#define I810_GFX_MEM_WIN_32M	0x00010000

#define I810_GFX_MEM_WIN_32M	0x00010000

drivers/char/agp/intel-gtt.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -176,7 +176,7 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem, 
	if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||

	if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||

	    agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)

	    agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)

	{

	{

		cache_bits = I830_PTE_SYSTEM_CACHED;

		cache_bits = GEN6_PTE_LLC_MLC;

	}

	}





	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {

	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {