Loading arch/arm/boot/dts/qcom/msm8996.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -3532,6 +3532,19 @@ <&clock_gcc clk_gcc_ce1_axi_m_clk>; qcom,ce-opp-freq = <171430000>; }; dcc: dcc@4b3000 { compatible = "qcom,dcc"; reg = <0x4b3000 0x1000>, <0x4b4000 0x2000>, <0x4b0000 0x4>; reg-names = "dcc-base", "dcc-ram-base", "dcc-xpu-base"; clocks = <&clock_gcc clk_gcc_dcc_ahb_clk>; clock-names = "dcc_clk"; qcom,save-reg; }; }; &gdsc_venus { Loading Loading
arch/arm/boot/dts/qcom/msm8996.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -3532,6 +3532,19 @@ <&clock_gcc clk_gcc_ce1_axi_m_clk>; qcom,ce-opp-freq = <171430000>; }; dcc: dcc@4b3000 { compatible = "qcom,dcc"; reg = <0x4b3000 0x1000>, <0x4b4000 0x2000>, <0x4b0000 0x4>; reg-names = "dcc-base", "dcc-ram-base", "dcc-xpu-base"; clocks = <&clock_gcc clk_gcc_dcc_ahb_clk>; clock-names = "dcc_clk"; qcom,save-reg; }; }; &gdsc_venus { Loading