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Commit a22a9a90 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Probe initrd header only if explicitly specified
  [MIPS] TX39xx: Add missing local_flush_icache_range initialization
  [MIPS] TXx9: Fix txx9_pcode initialization
  [MIPS] Fix WARNING: at kernel/smp.c:290
  [MIPS] Fix data bus error recovery
parents 70bb0896 0011036b

arch/mips/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -1886,6 +1886,15 @@ config STACKTRACE_SUPPORT 


source "init/Kconfig"



config PROBE_INITRD_HEADER

	bool "Probe initrd header created by addinitrd"

	depends on BLK_DEV_INITRD

	help

	  Probe initrd header at the last page of kernel image.

	  Say Y here if you are using arch/mips/boot/addinitrd.c to

	  add initrd or initramfs image to the kernel image.

	  Otherwise, say N.



menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"



config HW_HAS_EISA

arch/mips/kernel/setup.c

+18 −15
Original line number Diff line number Diff line
@@ -160,20 +160,20 @@ early_param("rd_size", rd_size_early); 
static unsigned long __init init_initrd(void)

{

	unsigned long end;

	u32 *initrd_header;



	/*

	 * Board specific code or command line parser should have

	 * already set up initrd_start and initrd_end. In these cases

	 * perfom sanity checks and use them if all looks good.

	 */

	if (initrd_start && initrd_end > initrd_start)

		goto sanitize;

	if (!initrd_start || initrd_end <= initrd_start) {

#ifdef CONFIG_PROBE_INITRD_HEADER

		u32 *initrd_header;



		/*

		 * See if initrd has been added to the kernel image by

		 * arch/mips/boot/addinitrd.c. In that case a header is

	 * prepended to initrd and is made up by 8 bytes. The fisrt

		 * prepended to initrd and is made up by 8 bytes. The first

		 * word is a magic number and the second one is the size of

		 * initrd.  Initrd start must be page aligned in any cases.

		 */
@@ -182,8 +182,11 @@ static unsigned long __init init_initrd(void) 
			goto disable;

		initrd_start = (unsigned long)(initrd_header + 2);

		initrd_end = initrd_start + initrd_header[1];

#else

		goto disable;

#endif

	}



sanitize:

	if (initrd_start & ~PAGE_MASK) {

		pr_err("initrd start must be page aligned\n");

		goto disable;

arch/mips/kernel/traps.c

+11 −7
Original line number Diff line number Diff line
@@ -373,8 +373,8 @@ void __noreturn die(const char * str, const struct pt_regs * regs) 
	do_exit(SIGSEGV);

}



extern const struct exception_table_entry __start___dbe_table[];

extern const struct exception_table_entry __stop___dbe_table[];

extern struct exception_table_entry __start___dbe_table[];

extern struct exception_table_entry __stop___dbe_table[];



__asm__(

"	.section	__dbe_table, \"a\"\n"
@@ -1200,7 +1200,7 @@ void *set_except_vector(int n, void *addr) 
	if (n == 0 && cpu_has_divec) {

		*(u32 *)(ebase + 0x200) = 0x08000000 |

					  (0x03ffffff & (handler >> 2));

		flush_icache_range(ebase + 0x200, ebase + 0x204);

		local_flush_icache_range(ebase + 0x200, ebase + 0x204);

	}

	return (void *)old_handler;

}
@@ -1283,7 +1283,8 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 
		*w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);

		w = (u32 *)(b + ori_offset);

		*w = (*w & 0xffff0000) | ((u32)handler & 0xffff);

		flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));

		local_flush_icache_range((unsigned long)b,

					 (unsigned long)(b+handler_len));

	}

	else {

		/*
@@ -1295,7 +1296,8 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 
		w = (u32 *)b;

		*w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */

		*w = 0;

		flush_icache_range((unsigned long)b, (unsigned long)(b+8));

		local_flush_icache_range((unsigned long)b,

					 (unsigned long)(b+8));

	}



	return (void *)old_handler;
@@ -1515,7 +1517,7 @@ void __cpuinit per_cpu_trap_init(void) 
void __init set_handler(unsigned long offset, void *addr, unsigned long size)

{

	memcpy((void *)(ebase + offset), addr, size);

	flush_icache_range(ebase + offset, ebase + offset + size);

	local_flush_icache_range(ebase + offset, ebase + offset + size);

}



static char panic_null_cerr[] __cpuinitdata =
@@ -1680,6 +1682,8 @@ void __init trap_init(void) 
	signal32_init();

#endif



	flush_icache_range(ebase, ebase + 0x400);

	local_flush_icache_range(ebase, ebase + 0x400);

	flush_tlb_handlers();



	sort_extable(__start___dbe_table, __stop___dbe_table);

}

arch/mips/mm/c-r3k.c

+1 −0
Original line number Diff line number Diff line
@@ -320,6 +320,7 @@ void __cpuinit r3k_cache_init(void) 
	flush_cache_range = r3k_flush_cache_range;

	flush_cache_page = r3k_flush_cache_page;

	flush_icache_range = r3k_flush_icache_range;

	local_flush_icache_range = r3k_flush_icache_range;



	flush_cache_sigtramp = r3k_flush_cache_sigtramp;

	local_flush_data_cache_page = local_r3k_flush_data_cache_page;

arch/mips/mm/c-r4k.c

+12 −6
Original line number Diff line number Diff line
@@ -543,12 +543,8 @@ struct flush_icache_range_args { 
	unsigned long end;

};



static inline void local_r4k_flush_icache_range(void *args)

static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)

{

	struct flush_icache_range_args *fir_args = args;

	unsigned long start = fir_args->start;

	unsigned long end = fir_args->end;



	if (!cpu_has_ic_fills_f_dc) {

		if (end - start >= dcache_size) {

			r4k_blast_dcache();
@@ -564,6 +560,15 @@ static inline void local_r4k_flush_icache_range(void *args) 
		protected_blast_icache_range(start, end);

}



static inline void local_r4k_flush_icache_range_ipi(void *args)

{

	struct flush_icache_range_args *fir_args = args;

	unsigned long start = fir_args->start;

	unsigned long end = fir_args->end;



	local_r4k_flush_icache_range(start, end);

}



static void r4k_flush_icache_range(unsigned long start, unsigned long end)

{

	struct flush_icache_range_args args;
@@ -571,7 +576,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end) 
	args.start = start;

	args.end = end;



	r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1);

	r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args, 1);

	instruction_hazard();

}
@@ -1375,6 +1380,7 @@ void __cpuinit r4k_cache_init(void) 
	local_flush_data_cache_page	= local_r4k_flush_data_cache_page;

	flush_data_cache_page	= r4k_flush_data_cache_page;

	flush_icache_range	= r4k_flush_icache_range;

	local_flush_icache_range	= local_r4k_flush_icache_range;



#if defined(CONFIG_DMA_NONCOHERENT)

	if (coherentio) {