Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a1f242ff authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Linus Torvalds
Browse files

powerpc ioremap_prot 



This adds ioremap_prot and pte_pgprot() so that one can extract protection
bits from a PTE and use them to ioremap_prot() (in order to support ptrace
of VM_IO | VM_PFNMAP as per Rik's patch).

This moves a couple of flag checks around in the ioremap implementations
of arch/powerpc.  There's a side effect of allowing non-cacheable and
non-guarded mappings on ppc32 which before would always have _PAGE_GUARDED
set whenever _PAGE_NO_CACHE is.

(standard ioremap will still set _PAGE_GUARDED, but ioremap_prot will be
capable of setting such a non guarded mapping).

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarRik van Riel <riel@redhat.com>
Cc: Dave Airlie <airlied@linux.ie>
Cc: Hugh Dickins <hugh@veritas.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 7ae8ed50

arch/powerpc/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ config PPC 
	select HAVE_DYNAMIC_FTRACE

	select HAVE_FTRACE

	select HAVE_IDE

	select HAVE_IOREMAP_PROT

	select HAVE_KPROBES

	select HAVE_ARCH_KGDB

	select HAVE_KRETPROBES

arch/powerpc/mm/pgtable_32.c

+16 −6
Original line number Diff line number Diff line
@@ -145,13 +145,20 @@ void pte_free(struct mm_struct *mm, pgtable_t ptepage) 
void __iomem *

ioremap(phys_addr_t addr, unsigned long size)

{

	return __ioremap(addr, size, _PAGE_NO_CACHE);

	return __ioremap(addr, size, _PAGE_NO_CACHE | _PAGE_GUARDED);

}

EXPORT_SYMBOL(ioremap);



void __iomem *

ioremap_flags(phys_addr_t addr, unsigned long size, unsigned long flags)

{

	/* writeable implies dirty for kernel addresses */

	if (flags & _PAGE_RW)

		flags |= _PAGE_DIRTY | _PAGE_HWWRITE;



	/* we don't want to let _PAGE_USER and _PAGE_EXEC leak out */

	flags &= ~(_PAGE_USER | _PAGE_EXEC | _PAGE_HWEXEC);



	return __ioremap(addr, size, flags);

}

EXPORT_SYMBOL(ioremap_flags);
@@ -163,6 +170,14 @@ __ioremap(phys_addr_t addr, unsigned long size, unsigned long flags) 
	phys_addr_t p;

	int err;



	/* Make sure we have the base flags */

	if ((flags & _PAGE_PRESENT) == 0)

		flags |= _PAGE_KERNEL;



	/* Non-cacheable page cannot be coherent */

	if (flags & _PAGE_NO_CACHE)

		flags &= ~_PAGE_COHERENT;



	/*

	 * Choose an address to map it to.

	 * Once the vmalloc system is running, we use it.
@@ -219,11 +234,6 @@ __ioremap(phys_addr_t addr, unsigned long size, unsigned long flags) 
		v = (ioremap_bot -= size);

	}



	if ((flags & _PAGE_PRESENT) == 0)

		flags |= _PAGE_KERNEL;

	if (flags & _PAGE_NO_CACHE)

		flags |= _PAGE_GUARDED;



	/*

	 * Should check if it is a candidate for a BAT mapping

	 */

arch/powerpc/mm/pgtable_64.c

+16 −0
Original line number Diff line number Diff line
@@ -107,9 +107,18 @@ void __iomem * __ioremap_at(phys_addr_t pa, void *ea, unsigned long size, 
{

	unsigned long i;



	/* Make sure we have the base flags */

	if ((flags & _PAGE_PRESENT) == 0)

		flags |= pgprot_val(PAGE_KERNEL);



	/* Non-cacheable page cannot be coherent */

	if (flags & _PAGE_NO_CACHE)

		flags &= ~_PAGE_COHERENT;



	/* We don't support the 4K PFN hack with ioremap */

	if (flags & _PAGE_4K_PFN)

		return NULL;



	WARN_ON(pa & ~PAGE_MASK);

	WARN_ON(((unsigned long)ea) & ~PAGE_MASK);

	WARN_ON(size & ~PAGE_MASK);
@@ -190,6 +199,13 @@ void __iomem * ioremap(phys_addr_t addr, unsigned long size) 
void __iomem * ioremap_flags(phys_addr_t addr, unsigned long size,

			     unsigned long flags)

{

	/* writeable implies dirty for kernel addresses */

	if (flags & _PAGE_RW)

		flags |= _PAGE_DIRTY;



	/* we don't want to let _PAGE_USER and _PAGE_EXEC leak out */

	flags &= ~(_PAGE_USER | _PAGE_EXEC);



	if (ppc_md.ioremap)

		return ppc_md.ioremap(addr, size, flags);

	return __ioremap(addr, size, flags);

include/asm-powerpc/io.h

+4 −1
Original line number Diff line number Diff line
@@ -617,7 +617,8 @@ static inline void iosync(void) 
 *   and can be hooked by the platform via ppc_md

 *

 * * ioremap_flags allows to specify the page flags as an argument and can

 *   also be hooked by the platform via ppc_md

 *   also be hooked by the platform via ppc_md. ioremap_prot is the exact

 *   same thing as ioremap_flags.

 *

 * * ioremap_nocache is identical to ioremap

 *
@@ -639,6 +640,8 @@ extern void __iomem *ioremap(phys_addr_t address, unsigned long size); 
extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size,

				   unsigned long flags);

#define ioremap_nocache(addr, size)	ioremap((addr), (size))

#define ioremap_prot(addr, size, prot)	ioremap_flags((addr), (size), (prot))



extern void iounmap(volatile void __iomem *addr);



extern void __iomem *__ioremap(phys_addr_t, unsigned long size,

include/asm-powerpc/pgtable-4k.h

+3 −0
Original line number Diff line number Diff line
@@ -51,6 +51,9 @@ 
#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \

			 _PAGE_SECONDARY | _PAGE_GROUP_IX)



/* There is no 4K PFN hack on 4K pages */

#define _PAGE_4K_PFN	0



/* PAGE_MASK gives the right answer below, but only by accident */

/* It should be preserving the high 48 bits and then specifically */

/* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */