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Commit a1ccbcd7 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Gerrit - the friendly Code Review server
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clk: msm: clock-mmss-8996: Set the NO_RATE_CACHE flag for display clocks 



Currently display branches do not propagate clk_set_rate() requests
to their parent if rate being set is same as its saved rate. With
the support to now change display RCG parents at run time, the
display clock tree requires these branch clocks to always propagate
request to their parents.
Add the CLKFLAG_NO_RATE_CACHE flag to display clocks to always pass
clk_set_rate() requests to their parents.

Change-Id: Ie2083fb082f1280134cc3611bca0e0d4396ddfa0
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 3e5d75b2

drivers/clk/msm/clock-mmss-8996.c

+12 −0
Original line number Diff line number Diff line
@@ -878,6 +878,7 @@ static struct rcg_clk pclk0_clk_src = { 
		.dbg_name = "pclk0_clk_src",

		.parent = &ext_pclk0_clk_src.c,

		.ops = &clk_ops_pixel_multiparent,

		.flags = CLKFLAG_NO_RATE_CACHE,

		VDD_DIG_FMAX_MAP3(LOWER, 175000000, LOW, 280000000,

							NOMINAL, 350000000),

		CLK_INIT(pclk0_clk_src.c),
@@ -916,6 +917,7 @@ static struct rcg_clk pclk1_clk_src = { 
		.dbg_name = "pclk1_clk_src",

		.parent = &ext_pclk1_clk_src.c,

		.ops = &clk_ops_pixel_multiparent,

		.flags = CLKFLAG_NO_RATE_CACHE,

		VDD_DIG_FMAX_MAP3(LOWER, 175000000, LOW, 280000000,

							NOMINAL, 350000000),

		CLK_INIT(pclk1_clk_src.c),
@@ -1398,6 +1400,7 @@ static struct rcg_clk byte0_clk_src = { 
		.dbg_name = "byte0_clk_src",

		.parent = &ext_byte0_clk_src.c,

		.ops = &clk_ops_byte_multiparent,

		.flags = CLKFLAG_NO_RATE_CACHE,

		VDD_DIG_FMAX_MAP3(LOWER, 131250000, LOW, 210000000,

							NOMINAL, 262500000),

		CLK_INIT(byte0_clk_src.c),
@@ -1435,6 +1438,7 @@ static struct rcg_clk byte1_clk_src = { 
		.dbg_name = "byte1_clk_src",

		.parent = &ext_byte1_clk_src.c,

		.ops = &clk_ops_byte_multiparent,

		.flags = CLKFLAG_NO_RATE_CACHE,

		VDD_DIG_FMAX_MAP3(LOWER, 131250000, LOW, 210000000,

							NOMINAL, 262500000),

		CLK_INIT(byte1_clk_src.c),
@@ -2459,6 +2463,7 @@ static struct branch_clk mdss_byte0_clk = { 
		.dbg_name = "mdss_byte0_clk",

		.parent = &byte0_clk_src.c,

		.ops = &clk_ops_branch,

		.flags = CLKFLAG_NO_RATE_CACHE,

		CLK_INIT(mdss_byte0_clk.c),

	},

};
@@ -2471,6 +2476,7 @@ static struct branch_clk mdss_byte1_clk = { 
		.dbg_name = "mdss_byte1_clk",

		.parent = &byte1_clk_src.c,

		.ops = &clk_ops_branch,

		.flags = CLKFLAG_NO_RATE_CACHE,

		CLK_INIT(mdss_byte1_clk.c),

	},

};
@@ -2559,6 +2565,7 @@ static struct branch_clk mdss_pclk0_clk = { 
		.dbg_name = "mdss_pclk0_clk",

		.parent = &pclk0_clk_src.c,

		.ops = &clk_ops_branch,

		.flags = CLKFLAG_NO_RATE_CACHE,

		CLK_INIT(mdss_pclk0_clk.c),

	},

};
@@ -2571,6 +2578,7 @@ static struct branch_clk mdss_pclk1_clk = { 
		.dbg_name = "mdss_pclk1_clk",

		.parent = &pclk1_clk_src.c,

		.ops = &clk_ops_branch,

		.flags = CLKFLAG_NO_RATE_CACHE,

		CLK_INIT(mdss_pclk1_clk.c),

	},

};
@@ -3746,12 +3754,16 @@ int msm_mmsscc_8996_probe(struct platform_device *pdev) 


	ext_pclk0_clk_src.dev = &pdev->dev;

	ext_pclk0_clk_src.clk_id = "pclk0_src";

	ext_pclk0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;

	ext_pclk1_clk_src.dev = &pdev->dev;

	ext_pclk1_clk_src.clk_id = "pclk1_src";

	ext_pclk1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;

	ext_byte0_clk_src.dev = &pdev->dev;

	ext_byte0_clk_src.clk_id = "byte0_src";

	ext_byte0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;

	ext_byte1_clk_src.dev = &pdev->dev;

	ext_byte1_clk_src.clk_id = "byte1_src";

	ext_byte1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;

	ext_extpclk_clk_src.dev = &pdev->dev;

	ext_extpclk_clk_src.clk_id = "extpclk_src";