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Commit a1b74afb authored by Hareesh Gundu's avatar Hareesh Gundu
Browse files

ARM: dts: msm: Update the DDR BW voting for msmtitanium 



Update the DDR BW voting to align GPU and DDR
voltage corners.

CRs-Fixed: 980532
Change-Id: Ie4c037fd7925dc12e3f5687bd4f4048f58c35b61
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
parent 73135edf

arch/arm/boot/dts/qcom/msmtitanium-gpu.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -146,7 +146,7 @@ 
			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <560000000>;

				qcom,bus-freq = <9>;

				qcom,bus-freq = <10>;

				qcom,bus-min = <8>;

				qcom,bus-max = <10>;

			};
@@ -155,7 +155,7 @@ 
			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <510000000>;

				qcom,bus-freq = <8>;

				qcom,bus-freq = <9>;

				qcom,bus-min = <6>;

				qcom,bus-max = <10>;

			};
@@ -165,26 +165,26 @@ 
				reg = <3>;

				qcom,gpu-freq = <400000000>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <9>;

				qcom,bus-min = <4>;

				qcom,bus-max = <8>;

			};



			/* SVS */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <320000000>;

				qcom,bus-freq = <5>;

				qcom,bus-min = <4>;

				qcom,bus-max = <7>;

				qcom,bus-freq = <4>;

				qcom,bus-min = <2>;

				qcom,bus-max = <6>;

			};



		       /* Low SVS */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <216000000>;

				qcom,bus-freq = <4>;

				qcom,bus-min = <2>;

				qcom,bus-max = <5>;

				qcom,bus-freq = <1>;

				qcom,bus-min = <1>;

				qcom,bus-max = <4>;

			};



			/* XO */